Strained channel complementary field-effect transistors

• US 7,442,967 B2
• Filed: 04/20/2006
• Issued: 10/28/2008
• Est. Priority Date: 08/12/2003
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Lee, Wen-Chin, Ko, Chih-Hsin, Hu, Chenming
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/407,633
• Publication Number:
  US 20060189056A1
• Time in Patent Office: 922 Days
• Field of Search: 257/174, 257/192, 257/338, 257/E29.193
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Claims

1. A transistor comprising:

a gate dielectric overlying a channel region;

a source region and a drain region on opposing sides of the channel region, the channel region comprising a first semiconductor material and the source and drain regions comprising a second semiconductor material, the first semiconductor material having a first lattice constant, the second semiconductor material having a second lattice constant different than the first lattice constant;

a gate electrode overlying the gate dielectric; and

first and second spacers formed on sides of the gate electrode, each of the spacers including a void adjacent the channel region.

2. The transistor of claim 1 and further comprising a high-stress film overlying the gate electrode and spacers.

3. The transistor of claim 1 wherein the high-stress film comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon oxide, and combinations thereof.

4. The transistor of claim 1 wherein each spacer includes a liner oxide and a spacer body.

5. The transistor of claim 4 wherein the void is disposed in the liner oxide of the spacer.

6. The transistor of claim 1 wherein the liner oxide comprises silicon oxide and the spacer body comprises silicon nitride.

7. The transistor of claim 1 wherein the transistor is a p-channel transistor.