Top layers of metal for high performance IC's
First Claim
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1. An integrated circuit chip comprising:
- a silicon substrate;
multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first and second contact points are separated from each other by an insulating material, and wherein said passivation layer comprises a nitride layer;
a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, and wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point; and
a second metallization structure on said polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises electroplated copper in said third opening and over said polymer layer.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
178 Citations
24 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first and second contact points are separated from each other by an insulating material, and wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, and wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point; and a second metallization structure on said polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, and wherein said second metallization structure comprises electroplated copper in said third opening and over said polymer layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said first metallization structure and exposes said contact point, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, and wherein a second opening in said polymer layer is over said contact point and exposes said contact point; and a second metallization structure on said contact point and on said polymer layer, wherein said second metallization structure is connected to said contact point through said second opening, and wherein said second metallization structure comprises electroplated copper over said polymer layer and in said second opening. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor in and on said silicon substrate; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a contact point of said first metallization structure, wherein said contact point is at a bottom of said first opening, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip; a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, and wherein a second opening in said polymer layer is over said contact point; a second metallization structure on said contact point and on said polymer layer, wherein said second metallization structure comprises electroplated copper over said polymer layer and in said second opening; and a solder over said second metallization structure and over said contact point, wherein said solder is connected to said contact point through said second metallization structure. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification