Self-biasing transistor structure and an SRAM cell having less than six transistors

• US 7,442,971 B2
• Filed: 01/28/2005
• Issued: 10/28/2008
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wirbeleit, Frank, Horstmann, Manfred, Hobert, Christian
• Primary Examiner(s): Dang, Phuc T
• Assistant Examiner(s): Tran, Thanh Y
• Application Number:
  US11/045,177
• Publication Number:
  US 20060022282A1
• Time in Patent Office: 1,369 Days
• Field of Search: 257/607, 257/408, 257/403, 257/344, 257/402, 257/241, 257/274, 257/287, 257/329, 438/289
• US Class Current: 257/287
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Claims

1. A semiconductor device, comprising:

a drain region formed in a substantially crystalline semiconductor material and doped with a first type of dopant material;

a source region formed in said substantially crystalline semiconductor material and doped with the first type of dopant material;

a first channel region located between said drain region and said source region and doped with the first type of dopant material;

a second channel region located between said drain region and said source region and adjacent to the first channel region and being doped with a second type of dopant material differing from said first type of dopant material, wherein the first channel region is disposed below said second channel region and said first type of dopant material results in a first type of conductivity and said second type of dopant material results in a second type of conductivity that is inverted with respect to said first type of conductivity; and

a gate electrode disposed above the first and second channel regions and located to enable control of the first and second channel regions, wherein said first and second channel regions in combination define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the first and second channel regions into a low impedance state and a second threshold voltage of the semiconductor device that results in an abrupt conductivity change of the total conductivity of said first and second channel regions when said total conductivity is in the low impedance state.

2. The semiconductor device of claim 1, further comprising a gate insulation layer that is in contact with said gate electrode and said second channel region.

3. The semiconductor device of claim 1, further comprising a conductive region connecting one of said drain region and said source region with said gate electrode.

4. The semiconductor device of claim 1, further comprising a select transistor having a drain terminal, a source terminal and a gate terminal, one of said drain and source terminals connected to said conductive region.

5. The semiconductor device of claim 4, wherein the other one of said drain and source terminal is connected to a read/write line and said gate electrode is connected to a select line.

6. The semiconductor device of claim 1, further comprising:

a second drain region formed in a second substantially crystalline semiconductor material and doped with the first type of dopant material;

a second source region formed in said second substantially crystalline semiconductor material and doped with the first type of dopant material;

a third channel region located between said second drain region and said second source region and doped with the first type of dopant material;

a fourth channel region located between said second drain region and said second source region and adjacent to said third channel region and being doped with the second type of dopant material differing from said first type; and

a second gate electrode located to enable control of the third and fourth channel regions, wherein the drain region, source region, first and second channel regions, and the gate electrode define a first transistor, and the second drain region, second source region, third and fourth channel regions, and second gate electrode define a second transistor.

7. The semiconductor device of claim 6, wherein said third and fourth channel regions in combination define a second threshold voltage for a second abrupt conductivity change of a total conductivity of said third and fourth channel regions when operated in a low impedance state.

8. The semiconductor device of claim 7, wherein the second threshold voltage differs from the first threshold voltage.

9. The semiconductor device of claim 1, wherein the first and second channel regions differ in at least one of material composition and internal strain.

10. The semiconductor device of claim 1, wherein said first type of dopant material results in a first type of conductivity and said second type of dopant material results in a second type of conductivity that is inverted to said first type of conductivity.

11. A static RAM cell, comprising:

a select transistor; and

an information storage element coupled to said select transistor, said information storage element including less than four transistor elements, wherein one of the transistor elements comprises a first controllable semiconductor device including at least;

a first drain region formed in a substantially crystalline semiconductor material and doped with a first type of dopant material;

a first source region formed in said substantially crystalline semiconductor material and doped with the first type of dopant material;

a first channel region located between said first drain region and said first source region and doped with the first type of dopant material;

a second channel region located between said first drain region and said first source region and adjacent to the first channel region and being doped with a second type of dopant material differing from said first type of dopant material, wherein the first channel region is disposed below said second channel region and said first type of dopant material results in a first type of conductivity and said second type of dopant material results in a second type of conductivity that is inverted with respect to said first type of conductivity; and

a first gate electrode disposed above the first and second channel regions and located to enable control of the first and second channel regions, wherein said first and second channel regions in combination define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the first and second channel regions into a low impedance state and a second threshold voltage of the semiconductor device that results in an abrupt conductivity change of the total conductivity of said first and second channel regions when said total conductivity is in the low impedance state.

12. The static RAM cell of claim 11, wherein said first controllable semiconductor device has at least one stationary conductive state and said first gate electrode is configured to control a conductivity of said first and second channel regions, one of said first source region and said first drain region being connected to said first gate electrode and being configured to self-bias said first gate electrode when said first controllable semiconductor device is in said at least one stationary conductive state.

13. The static RAM cell of claim 12, wherein said first and second channel regions are formed between said first drain region and said first source region and are configured to define at least a first threshold for an absolute amount of voltage applied to the first gate electrode, said first threshold being a lower limit for a gate voltage to transit into said self biased at least one stationary conductive state.

14. The static RAM cell of claim 12, wherein said information storage element comprises a second controllable semiconductor device having at least one stationary conductive state and having a second source region, a second drain region, a third channel region formed therebetween, and a second gate electrode configured to control a conductivity of said third channel region, at least one of said second source region and said second drain region being connected to said second gate electrode and being configured to self-bias said second gate electrode when said second controllable semiconductor device is in said at least one stationary conductive state.

15. The static RAM cell of claim 14, wherein said second controllable semiconductor device is operable in a self-biased state with a second control voltage that differs from a first control voltage required to operate said first controllable semiconductor device in a self-biased state.

16. The static RAM cell of claim 11, wherein said first and second channel regions differ in at least one of material composition and internal strain.

17. A static RAM cell, comprising:

a transistor element having a gate electrode, a drain region formed in a substantially crystalline semiconductor material and doped with a first type of dopant material, a source region formed in said substantially crystalline semiconductor material and doped with the first type of dopant material, a channel region electrically connected with said gate electrode and controllable by said gate electrode, the channel region including a first sub-region doped with the first type of dopant material and a second sub-region doped with a second type of dopant material differing from said first type of dopant material, wherein the gate electrode is disposed above the first and second channel regions, the first channel region is disposed below said second channel region, said first type of dopant material results in a first type of conductivity and said second type of dopant material results in a second type of conductivity that is inverted with respect to said first type of conductivity, said first and second channel regions in combination define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the first and second channel regions into a low impedance state and a second threshold voltage of the semiconductor device that results in an abrupt conductivity change of the total conductivity of said first and second channel regions when said total conductivity is in the low impedance state, and said transistor element is configured to self-bias said gate electrode to maintain said channel region in a stationary conductive state.

18. The static RAM cell of claim 17, further comprising a select transistor element coupled to said transistor element.

19. The static RAM cell of claim 18, wherein a total number of transistor elements is less than six.

20. The static RAM cell of claim 17, wherein said channel region is formed between said drain region and said source region and is configured to define at least a first threshold for an absolute amount of voltage applied to the gate electrode, said first threshold being a lower limit for a gate voltage to transit into said self-biased stationary conductive state.

21. The static RAM cell of claim 17, wherein said transistor element further comprises a doped semiconductor region having a conductivity type and being located adjacent to said drain region, source region and said channel region, said conductivity type differing from a conductivity type of said drain region and source region.

22. The static RAM cell of claim 17, wherein said transistor element further comprises an insulation layer formed adjacent to said drain and source regions and said channel region, said insulation layer isolating said transistor element from a substrate.

23. The static RAM cell of claim 17, wherein said first and second sub-regions differ in at least one of material composition and internal strain.

24. The static RAM cell of claim 17, further comprising a second transistor element having at least one self-biased stationary conductive state and having a second channel region and a second gate electrode configured to control a conductivity of said second channel region, said second channel region connected to said second gate electrode and being configured to self-bias said second gate electrode when said transistor element is in said at least one self-biased stationary conductive state.

25. A static RAM cell comprising two or less transistor elements wherein at least one of the two or less transistor elements is a double channel transistor element that includes at least:

a drain region formed in a substantially crystalline semiconductor material and doped with a first type of dopant material;

a source region formed in said substantially crystalline semiconductor material and doped with the first type of dopant material;

a first channel region located between said drain region and said source region and doped with the first type of dopant material;

a second channel region located between said drain region and said source region and adjacent to the first channel region and being doped with a second type of dopant material differing from said first type of dopant material, wherein the first channel region is disposed below said second channel region and said first type of dopant material results in a first type of conductivity and said second type of dopant material results in a second type of conductivity that is inverted with respect to said first type of conductivity; and

a gate electrode disposed above the first and second channel regions and located to enable control of the first and second channel regions, wherein said first and second channel regions in combination define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the first and second channel regions into a low impedance state and a second threshold voltage of the semiconductor device that results in an abrupt conductivity change of the total conductivity of said first and second channel regions when said total conductivity is in the low impedance state.