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Self-biasing transistor structure and an SRAM cell having less than six transistors

  • US 7,442,971 B2
  • Filed: 01/28/2005
  • Issued: 10/28/2008
  • Est. Priority Date: 07/30/2004
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a drain region formed in a substantially crystalline semiconductor material and doped with a first type of dopant material;

    a source region formed in said substantially crystalline semiconductor material and doped with the first type of dopant material;

    a first channel region located between said drain region and said source region and doped with the first type of dopant material;

    a second channel region located between said drain region and said source region and adjacent to the first channel region and being doped with a second type of dopant material differing from said first type of dopant material, wherein the first channel region is disposed below said second channel region and said first type of dopant material results in a first type of conductivity and said second type of dopant material results in a second type of conductivity that is inverted with respect to said first type of conductivity; and

    a gate electrode disposed above the first and second channel regions and located to enable control of the first and second channel regions, wherein said first and second channel regions in combination define a first threshold voltage of the semiconductor device for transitioning a total conductivity of the first and second channel regions into a low impedance state and a second threshold voltage of the semiconductor device that results in an abrupt conductivity change of the total conductivity of said first and second channel regions when said total conductivity is in the low impedance state.

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