On-chip probing apparatus

• US 7,443,180 B2
• Filed: 12/06/2006
• Issued: 10/28/2008
• Est. Priority Date: 12/06/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mutnury, Bhyrav M., Pham, Nam H., Cases, Moises, Herrman, Bradley D., de Araujo, Daniel N., Patel, Pravin S., Matoglu, Erdem
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): BENITEZ ROSARIO, JOSHUA
• Application Number:
  US11/567,449
• Publication Number:
  US 20080136427A1
• Time in Patent Office: 692 Days
• Field of Search: 324754-765
• US Class Current: 324/756.05
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.

Claims

1. An on-chip probing apparatus, comprising:

a plurality of externally accessible probe points on a chip, wherein each probe point is associated with, and selectively connectable to, a different pair of output signals of the chip;

a switching circuit coupled to each probe point and the pair of output signals associated with the probe point, the switching circuit comprising a first switch for selectively connecting a first of the pair of output signals to the probe point and a second switch for selectively connecting a second of the pair of output signals to the probe point;

a multiplexer for controlling the first and second switches in each switching circuit to selectively connect an output signal of the chip to a respective probe point on the chip; and

a package for the chip;

wherein the package includes a plurality of external probe points for accessing the probe points on the chip, and a plurality of signal pins, separate from the external probe points, for accessing the output signals of the chip.

2. The apparatus of claim 1, wherein the plurality of switches on the chip comprise complementary metal-oxide semiconductor (CMOS) switches.

3. The apparatus of claim 1, further comprising:

a plurality of signal traces in the package for providing external access to the probe points on the chip and the output signals of the chip.

4. An integrated circuit, comprising:

a plurality of externally accessible probe points on the integrated circuit, wherein each probe point is associated with, and selectively connectable to, a different pair of output signals of the integrated circuit;

a switching circuit coupled to each probe point and the pair of output signals associated with the probe point, the switching circuit comprising a first switch for selectively connecting a first of the pair of output signals to the probe point and a second switch for selectively connecting a second of the pair of output signals to the probe point;

a multiplexer for controlling the first and second switches in each switching circuit to selectively connect an output signal of the integrated circuit to a respective probe point on the chip; and

a package for the integrated circuit;

wherein the package includes a plurality of external probe points for accessing the probe points on the integrated circuit, and a plurality of signal pins, separate from the external probe points, for accessing the output signals of the integrated circuit.

5. The integrated circuit of claim 4, wherein the plurality of switches on the chip comprise complementary metal-oxide semiconductor (CMOS) switches.

6. The integrated circuit of claim 4, further comprising:

a plurality of signal traces in the package for providing external access to the probe points on the chip and the output signals of the chip.