On-wafer test structures for differential signals

• US 7,443,186 B2
• Filed: 03/09/2007
• Issued: 10/28/2008
• Est. Priority Date: 06/12/2006
• Status: Expired due to Fees

• Current Assignee: FormFactor Beaverton, Inc. (FormFactor Incorporated)
• Original Assignee: Cascade Microtech Incorporated (FormFactor Incorporated)
• Inventors: Campbell, Richard, Strid, Eric
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): Kusumakar; Karen M
• Application Number:
  US11/716,428
• Publication Number:
  US 20070285112A1
• Time in Patent Office: 599 Days
• Field of Search: 324/754, 324/763, 324/765, 257/48
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

A test structure for characterizing integrated circuits on a wafer includes a differential cell outputting a differential mode signal in response to a differential mode input signal. The probe pads of the test structure are arrayed linearly enabling placement of the test structure in a saw street between dies.

Claims

1. A test structure for characterizing a circuit fabricated on a substrate, said test structure comprising:

(a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to application of a transistor bias voltage to a bias terminal and application of a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to application of said bias voltage to said bias terminal and application of a differential input signal applied to said first signal terminal and said second signal terminal;

(b) a first probe pad interconnected with said third signal terminal;

(c) a second probe pad adjacent to said first probe pad and interconnected with said first signal terminal;

(d) a third probe pad adjacent to said second probe pad and interconnected with said bias terminal;

(e) a fourth probe pad adjacent to said third probe pad and interconnected to said second signal terminal; and

(f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said fourth signal terminal.

2. The test structure of claim 1 wherein said first, said second, said third, said fourth and said fifth probe pads are located within a saw street bounded by a first die and a second die.

3. The test structure of claim 1 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said first probe pad is inverted relative to said phase of said signal at said second probe pad.

4. The test structure of claim 1 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first input signal, and said phase of said signal at said first probe pad is the same as said phase of said signal at said second probe pad.

5. The test structure of claim 1 wherein said first, said second, said third, said fourth and said fifth probe pads are arrayed substantially linearly on said wafer.

6. The test structure of claim 5 wherein said probe pads of said linear array are located within a saw street bounded a first die and a second die fabricated on said substrate.

7. A test structure for characterizing a circuit fabricated on a substrate, said test structure comprising:

(a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to application of a transistor bias voltage to a bias terminal and application of a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to application of said bias voltage to said bias terminal and application of a differential input signal applied to said first signal terminal and said second signal terminal;

(b) a first probe pad interconnected to said bias terminal;

(c) a second probe pad adjacent to said first probe pad and interconnected with said third signal terminal;

(d) a third probe pad adjacent to said second probe pad and interconnected with said first signal terminal;

(e) a fourth probe pad adjacent to said third probe pad and interconnected with said bias terminal;

(f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said second signal terminal;

(g) a sixth probe pad adjacent to said fifth probe pad and interconnected to said fourth signal terminal;

(h) a seventh probe pad adjacent to said sixth probe pad and interconnected to said bias terminal.

8. The test structure of claim 7 wherein said first, said second, said third, said fourth, said fifth, said sixth and said seventh probe pads are located within a saw street bounded by a first die and a second die.

9. The test structure of claim 7 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is inverted relative to said phase of said signal at said third probe pad.

10. The test structure of claim 7 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is the same as said phase of said signal at said third probe pad.

11. The test structure of claim 7 wherein said first, said second, said third, said fourth and said fifth, said sixth and said seventh probe pads are arrayed substantially linearly on said wafer.

12. The test structure of claim 11 wherein said probe pads of said linear array are located within a saw street bounded a first die and a second die fabricated on said substrate.

13. A test structure for characterizing a circuit fabricated on a substrate, said test structure comprising:

(a) a differential cell to output a differential output signal at a first signal terminal and a second signal terminal in response to application of a transistor bias voltage to a bias terminal and application of a differential input signal applied to a third signal terminal and a fourth signal terminal and, alternatively, to output a differential output signal at said third signal terminal and said fourth signal terminal in response to application of said bias voltage to said bias terminal and application of a differential input signal applied to said first signal terminal and said second signal terminal;

(b) a first probe pad interconnected to said bias terminal;

(c) a second probe pad adjacent to said first probe pad and interconnected with said third signal terminal;

(d) a third probe pad adjacent to said second probe pad and interconnected with said first signal terminal;

(e) a fourth probe pad adjacent to said third probe pad and interconnected to said second signal terminal;

(f) a fifth probe pad adjacent to said fourth probe pad and interconnected to said fourth signal terminal; and

(g) a sixth probe pad proximate said fifth probe pad and interconnected to said bias terminal.

14. The test structure of claim 13 wherein said first, said second, said third, said fourth, said fifth and said sixth probe pads are located within a saw street bounded by a first die and a second die.

15. The test structure of claim 13 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is inverted relative to said phase of said signal at said third probe pad.

16. The test structure of claim 13 wherein said differential input signal comprises a first input signal and a second input signal, said second input signal having a phase opposite said first input signal, and said differential output signal comprises a first output signal and a second output signal, said second output signal having a phase opposite said first output signal, and said phase of said signal at said second probe pad is the same as said phase of said signal at said third probe pad.

17. The test structure of claim 13 wherein said first, said second, said third, said fourth and said fifth and said sixth probe pads are arrayed substantially linearly on said wafer.

18. The test structure of claim 17 wherein said probe pads of said linear array are located within a saw street bounded a first die and a second die fabricated on said substrate.