Level shifting circuit

• US 7,443,223 B2
• Filed: 08/31/2006
• Issued: 10/28/2008
• Est. Priority Date: 08/31/2006
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hoekstra, George P., Ghassemi, Hamed, Bajkowski, Maciej
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US11/468,815
• Publication Number:
  US 20080054980A1
• Time in Patent Office: 789 Days
• Field of Search: 327/306, 327/333, 326 80- 81, 326 62- 64, 326/68
• US Class Current: 327/333
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence

Abstract

A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Claims

1. A circuit comprising:

a clocked level shifter including a signal input, the signal input is coupled to an output of circuitry, the signal input for operating within a first voltage domain, the clocked level shifter including a signal output for operating within a second voltage domain that differs from the first voltage domain, wherein the clocked level shifter includes a clock input for receiving a clock signal, wherein the clock signal has a pulse time with a duration that is shorter than clock phase durations of a second clock signal received by the circuitry and used to provide information to the signal input;

a latch coupled to an output of the clocked level shifter.

2. The circuit of claim 1 wherein the clocked level shifter further comprises:

a level shifting stack of series-connected transistors wherein two of the series-connected transistors are of opposite conductivity types and include a control electrode coupled to the signal input, the level shifting stack including another of the series-connected transistors including a control electrode coupled to clock input.

3. The circuit of claim 1 wherein the clock signal has a pulse time with a duration that is independent of clock phase durations of a second clock signal used to provide information to the signal input.

4. The circuit of claim 1 wherein the clock signal has a pulse time with a duration that is independent of a duration of a clock phase of a second clock signal used to generate the pulse time.

5. The circuit of claim 1 wherein the clock signal has a pulse time with a duration that is shorter than a duration of a clock phase of a second clock signal used to generate the pulse time.

6. The circuit of claim 1 wherein the clock signal has a frequency that is less than a frequency a second clock signal used to provide information to the signal input.

7. The circuit of claim 1 wherein the clock signal has a frequency which is less than a frequency a second clock signal used to generate the clock signal.

8. The circuit of claim 1 wherein the clocked level shifter further comprises:

a level shifting stack of series-connected transistors wherein a first transistor of the series-connected transistors includes a control electrode coupled to the signal input and has a threshold voltage that is greater in magnitude than a threshold voltage of at least some of a remainder of the series-connected transistors.

9. The circuit of claim 8 wherein the first transistor is a P-channel type MOSFET.

10. A circuit comprising:

a clocked level shifter including a signal input, the signal input for operating within a first voltage domain, the signal input is coupled to an output of circuitry, the clocked level shifter including a signal output for operating within a second voltage domain that differs from the first voltage domain, wherein the clocked level shifter includes a clock input for receiving a clock signal, wherein the clock signal has a pulse time with a duration that is shorter than clock phase durations of a second clock signal received by the circuitry and used to provide information to the signal input;

a latch coupled to an output of the clocked level shifter;

wherein the clocked level shifter further comprises;

a first transistor of a first conductivity type including a first current electrode coupled to a power supply terminal of the second voltage domain, a control electrode coupled to the signal input and for operating within the first voltage domain, and a second current electrode;

a second transistor of the first conductivity type having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the clock signal, and a second current electrode coupled to the signal output;

a third transistor of a second conductivity type having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving an inverse signal of the clock signal, and a second current electrode; and

a fourth transistor of the second conductivity type having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the signal input and for operating within the first voltage domain, and a second current electrode coupled to a second power supply terminal.

11. The circuit of claim 10 wherein the clock signal has a pulse time with a duration that is shorter than clock phase durations of a second clock signal used to provide information to the signal input.

12. The circuit of claim 10 further comprising:

a latch circuit including the clocked level shifter and the latch;

a master latch circuit having an output coupled to the signal input wherein the latch circuit is characterized as a slave latch circuit to the master latch circuit.

13. The circuit of claim 10 wherein the first transistor has a threshold voltage that is greater in magnitude than a threshold voltage of each of the third transistor and the fourth transistor.

14. A method, comprising:

providing a signal input for receiving an input signal, the input signal operating in a first voltage domain, the signal input is coupled to an output of circuitry;

providing a pair of transistors of opposite conductivity type coupled in series, each transistor of the pair including a control electrode coupled to the signal input and for operating in the first voltage domain, the pair of transistors of opposite conductivity type providing an output signal at a signal output, the output signal operating in a second voltage domain, wherein the second voltage domain differs from the first voltage domain;

providing a latch coupled to the signal output for latching the output signal; and

providing a P-channel transistor coupled in series with the pair of transistors of opposite conductivity type, the P-channel transistor having a control electrode for receiving a first signal to electrically isolate the signal output from a power supply terminal of the second voltage domain, wherein the first signal has a pulse time with a duration that is shorter than clock phase durations of a clock signal received by the circuitry and used to provide information to the signal input.

15. The method of claim 14 further wherein the providing a pair of transistors includes providing a P-channel transistor of the pair of transistors with a threshold voltage that is larger than a threshold voltage of a corresponding N-channel transistor of the pair of transistors.

16. A level shifting circuit comprising:

a signal input for receiving a signal in a first voltage domain, the signal input is coupled to an output of circuitry; and

a clocked level shifter coupled to the signal input and to a power supply terminal for receiving a supply voltage different from the first voltage domain, the clocked level shifter includes a signal output for providing an output signal and a clock input for receiving a clock signal for electrically isolating the power supply terminal from the signal output, wherein the clocked level shifter includes a stack of series connected transistors with two transistors of the stack of series connected transistors having control electrodes coupled to the signal input and for operating in the first voltage domain, wherein the stack of series connected transistors includes a P-channel transistor having a control electrode coupled to the clock input, wherein the clock signal has a pulse time with a duration that is shorter than clock phase durations of a second clock signal received by the circuitry and used to provide information to the signal input.

17. The level shifting circuit of claim 16 wherein the level shifting circuit is configured such that the clock signal electrically isolates the power supply terminal from the signal output for a portion of a clock cycle of a second clock signal used for controlling information flow to the signal input.

18. The level shifting circuit of claim 16 wherein the stack of series connected transistors further comprises:

a first transistor of a first conductivity type including a first current electrode coupled to the power supply terminal, a control electrode for receiving the clock signal, and a second current electrode, wherein the first transistor is the P-channel transistor;

a second transistor of the first conductivity type including a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the signal input, and a second current electrode coupled to the signal output;

a third transistor of a second conductivity type opposite the first conductivity type and including a first current electrode coupled to the signal output, a control electrode coupled to the signal input, and a second current electrode coupled to a second power supply terminals;

wherein the second and third transistors are the two transistors.

19. The level shifting circuit of claim 18 wherein the second transistor is a P-channel transistor and has a threshold voltage that is larger than a threshold voltage of the third transistor.

20. The level shifting circuit of claim 16 wherein stack of series connected transistors further comprises:

a first transistor of a first conductivity type including a first current electrode coupled to the power supply terminal, a control electrode coupled to the signal input, and a second current electrode;

a second transistor of the first conductivity type including a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the clock signal, and a second current electrode coupled to the signal output wherein the second transistor is the p-channel transistor;

a third transistor of a second conductivity type opposite the first conductivity type and including a first current electrode coupled to the signal output, a control electrode coupled to a complementary clock signal of the clock signal and a second current electrode;

a fourth transistor of the second conductivity type including a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the signal input, and a second current electrode coupled to a second power supply terminal;

wherein the first and fourth transistors are the two transistors.

21. The level shifting circuit of claim 16 further comprising a latch coupled to the signal output for latching a signal of the signal output.

22. The level shifting circuit of claim 16 wherein the supply voltage is of a higher voltage than the voltage of the first voltage domain.