Self testing ground fault circuit interrupter (GFCI)

• US 7,443,309 B2
• Filed: 12/01/2004
• Issued: 10/28/2008
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Hubbell, Inc.
• Original Assignee: Hubbell, Inc.
• Inventors: Bonilla, Nelson, Yu, David, Baldwin, John R.
• Primary Examiner(s): Nguyen; Hung T.
• Application Number:
  US11/000,531
• Publication Number:
  US 20060125622A1
• Time in Patent Office: 1,427 Days
• Field of Search: 340/650, 340/657, 340/514, 340/635, 340/649, 340/654, 340/664, 361/42, 361/45, 361/49, 361/50, 361/71, 361/73, 361/93.1, 361/44, 324/709, 324/713
• US Class Current: 340/650
• CPC Class Codes: H01H 2071/044 Monitoring, detection or measuring systems to establish the end of life of the switching device, can also contain other on-line monitoring systems, e.g. for detecting mechanical failures
• CPC Class Codes: H01H 83/04 with testing means for indicating the ability of the switch or relay to function properly
• CPC Class Codes: H01H 9/56 for ensuring operation of the switch at a predetermined point in the ac cycle

Abstract

A self testing fault detector having a line side and a load side and a conductive path there between, said apparatus is provided. The self testing fault detector includes a controller, adapted to perform periodic status tests on a protection circuit of the self testing fault detector without interrupting power to the load.

Claims

1. A self testing fault detector having a line side adapted to receive a sinusoidal input signal, a load side adapted for connection to a load and a conductive path there between, said apparatus comprising:

a controller, adapted to perform periodic self tests to determine a status of a protection circuit of said self testing fault detector without interrupting power to said load side; and

a capacitor having a terminal connected between a solenoid and a switching device of the protection circuit;

wherein the capacitor is charged through the solenoid during positive half-cycles of the input signal and discharges at a first rate when the switching device is on and at a second rate, different from the first rate, when the switching device is off, during negative half-cycles of the input signal; and

wherein the controller detects operability of the protection circuit by detecting a discharge of the capacitor at the first rate.

2. The self testing fault detector of claim 1, wherein said controller is

further adapted to cause an imbalance in a ground fault detection circuit and detect an output signal of a ground fault circuit interrupter (GFCI) chip.

3. The self testing fault detector of claim 2, wherein said controller is adapted cause said imbalance only during negative half cycles of said sinusoidal input signal.

4. The self testing fault detector of claim 2, wherein said controller determines that said self testing fault detector is faulty if said output signal of said GFCI is not detected by said controller.

5. The self testing fault detector of claim 1, wherein said switching device comprises a Silicon Controlled Rectifier (SCR).

6. The self testing fault detector of claim 1, wherein said SCR is adapted to energize a solenoid when activated during positive half cycles of said sinusoidal input signal.

7. The self testing fault detector of claim 1, wherein said controller determines that the solenoid has continuity if the controller detects that said capacitor is charged during a negative half cycle of said sinusoidal input signal.

8. The self testing fault detector of claim 1, wherein said periodic self tests are performed at one minute intervals.

9. The self testing fault detector of claim 1, wherein said controller activates the protection circuit if a signal from a ground fault circuit interrupter (GFCI) chip is not detected.

10. A method for performing a self test on a fault detector having a line side adapted to receive a sinusoidal input signal, and a load side adapted for connection to a load, and a conductive path there between, comprising:

performing periodic self tests to determine a status of a protection circuit of said self testing fault detector without interrupting power to said load side;

said self tests comprising detecting a discharge rate of a capacitor during a negative half-cycle of the input signal;

said capacitor being charged through a solenoid of the protection circuit during positive half-cycles of the input signal, and discharged at a first rate during the negative half-cycle of the input signal when a switching device is turned on, and discharged at a second rate, slower than the first rate, during the negative half-cycle of the input signal when the switching device is turned off.

11. The method of claim 10, further comprising:

causing an imbalance in a detection circuit and detecting an output signal of a ground fault circuit interrupter (GFCI) chip.

12. The method of claim 11, wherein the step of providing further comprising:

causing the imbalance only during negative half cycles of said sinusoidal input signal.

13. The method of claim 11, further comprising:

determining that said fault detector is faulty if said output signal of said GFCI chip is not detected.

14. The method of claim 10, further comprising:

activating the switching device and determining if a current flows in said switching device.

15. The method of claim 14, wherein said switching device comprises a Silicon Controlled Rectifier (SCR).

16. The method of claim 10, further comprising:

determining that a solenoid has continuity if a charge is detected in said capacitor during a negative half cycle of said sinusoidal input.

17. The method of claim 10, further comprising:

performing said periodic self tests at one minute intervals.

18. The method of claim 10, further comprising:

activating the protection circuit if a signal from a ground fault circuit interrupter (GFCI) chip is not detected.

19. A self testing fault detector having a line side and a load side and a conductive path there between, said apparatus comprising:

a solenoid, adapted to move a miswire prevention plate from a first position operable to prevent closure of at least one contact disposed in said conductive path, to a second position operable to allow closure of said at least one contact when said self testing fault detector is powered from the line side; and

a processor, adapted to perform a periodic self test to determine a status of the self testing fault detector without interrupting power to the load side.

20. The self testing fault detector of claim 19, wherein said periodic test comprises testing at least one of a GFCI chip, a solenoid, and a switch.

21. The self testing fault detector of claim 20, wherein said first switch comprises a silicon controlled rectifier (SCR).

22. The self testing fault detector of claim 21, wherein said controller opens said

at least one contact by signaling said SCR if a GFCI chip fails to open said at least one contact.

23. The self testing fault detector of claim 22, wherein said at least one contact is resettable to provide electrical continuity for said self testing fault detector.

24. The self testing fault detector of claim 19, further comprising a ground fault circuit interrupter (GFCI) chip adapted to open at least one contact if a ground fault is detected.

25. The self testing fault detector of claim 24, wherein the GFCI chip energizes the solenoid to open the at least one contact.

26. The self testing fault detector of claim 19, wherein said periodic self test occurs at one minute intervals.

27. The self testing fault detector of claim 19, further comprises an alarm indicator.

28. The self testing fault detector of claim 27, wherein said alarm indicator comprises a green LED to indicate normal operation of said self testing fault detector.

29. The self testing fault detector of claim 27, wherein said alarm indicator comprises a red LED to indicate a fault.

30. The self testing fault detector of claim 29, wherein said red LED flashes upon failure of the self test and illuminates solid upon the opening of the at least one contact during a manual test or detection of an actual ground fault.

31. The self testing fault detector of claim 19, wherein said periodic self test occurs during a negative half cycle of a sinusoidal input signal.