Communication protocol system and method

• US 7,443,886 B1
• Filed: 04/30/2002
• Issued: 10/28/2008
• Est. Priority Date: 04/30/2002
• Status: Expired due to Term

• Current Assignee: Schneider Automation Incorporated (Schneider Electric SE)
• Original Assignee: Schneider Automation Incorporated (Schneider Electric SE)
• Inventors: Gross, Ronald
• Primary Examiner(s): Patel; Ajit
• Application Number:
  US10/137,192
• Time in Patent Office: 2,373 Days
• Field of Search: 370/465, 370/474, 370/476, 370/389, 370/392, 370/254, 709/208, 709/209
• US Class Current: 370/476
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling

Abstract

A communication protocol comprising a data packet, a control byte, and a check sum byte. The data packet having a plurality of data words wherein each data word comprises a first byte and a second byte. The control byte having a first address bit, a second address bit, and a third address bit for identifying an address of a slave controller, a type bit following the first address bit, the second address bit, and the third address bit for identifying a data type within said data packet, a direction bit following the type bit for identifying a source of the data frame, a content bit following the direction bit for identifying whether said data packet comprises data, a state bit following the content bit for identifying a state of a master controller, and a run/stop bit following the state bit for identifying a run/stop state of the master controller. The protocol comprises a check sum byte to ensure correct transmission of the data packet and control byte.

Claims

1. A system for implementing a communication protocol for facilitating transmission of a data frame having a control byte, a data packet, and a check sum byte, comprising:

a master controller communicatively coupled to a slave controller, wherein communication between the master controller and the slave controller includes transmission of a control byte having

a first address bit, second address bit, and third address bit for identifying an address of a slave controller;

a type bit immediately following the first address bit, the second address bit, and the third address bit for identifying a data type in a data packet;

a direction bit immediately following the type bit for identifying a source of a data frame;

a content bit immediately following the direction bit for identifying whether said data packet comprises data;

a state bit immediately following the content bit for identifying a state of the master controller; and

,

a run/stop bit immediately following the state bit for identifying a run/stop state of the master controller.

2. The system of claim 1, wherein the type bit identifies said data type as input/output data when set to 0 and identifies said data type as application data when set to 1.

3. The system of claim 1, wherein the direction bit identifies the source of said data frame as the master controller when set to 0 and identifies the source of the data frame as a slave controller when set to 1.

4. The system of claim 1, wherein the content bit indicates that said data packet contains data when set to 1 and indicates that said data packet contains no data when set to 1.

5. The system of claim 1, wherein the run/stop bit indicates that the master controller is stopped when set to 0 and indicates that the master controller is running when set to 1.

6. The system of claim 1, wherein the data frame comprises the data packet having a plurality of data words.

7. The system of claim 1, wherein the data packet comprises a first data word, a second data word, a third data word, and a fourth data word, wherein each data word comprises a first byte and a second byte.

8. The system of claim 1, wherein the data frame comprises a check sum byte comprising a two'"'"'s complement ADD check of the control byte and the data packet.

9. A system for implementing a communication protocol for facilitating a transmission of a data frame between a master controller and a slave controller, comprising:

a master controller communicatively coupled to a slave controller, wherein communication between the master controller and the slave controller includes transmission of;

a data packet having a plurality of data words wherein each data word comprises a first byte and a second byte;

a control byte having a first address bit, a second address bit, and a third address bit for identifying an address of a slave controller, a type bit following the first address bit, the second address bit, and the third address bit for identifying a data type within said data packet, a direction bit following the type bit for identifying a source of a data frame, a content bit following the direction bit for identifying whether said data packet comprises data, a state bit following the content bit for identifying a state of a master controller, and a run/stop bit following the state bit for identifying a run/stop state of the master controller; and

,

a check sum byte.

10. The system of claim 9, wherein the type bit identifies the data type as input/output data when set to 0 and identifies the data type as application data when set to 1.

11. The system of claim 9, wherein the direction bit identifies the source of the data as the master controller when set to 0 and identifies the source of the data as the slave controller when set to 1.

12. The system of claim 9, wherein the content bit indicates that the data packet contains data when set to 0 and indicates that the data packet contains no data when set to 1.

13. The system of claim 9, wherein the run/stop bit indicates that the master controller is stopped when set to 0 and indicates that the master controller is running when set to 1.

14. The system of claim 9, wherein the data packet comprises a first data word, a second data word, a third data word, and a fourth data word, wherein each data word comprises a first byte and a second byte.

15. The system of claim 9, wherein the check byte is a two'"'"'s complement ADD check of the control byte and the data words.

16. A master controller for transmitting a data frame to a slave controller, the master controller comprising:

means for generating a data frame wherein the data frame comprises a control byte comprising a first address bit, a second address bit, and a third address bit for identifying a slave controller, a type bit following the first address bit, the second address bit, and the third address bit for identifying a data type in a data packet, a direction following the type bit for identifying a source of the data frame, a content bit following the direction bit for identifying whether the data packet comprises data, a state bit following the content bit for identifying the state of a master controller, and a run/stop bit following the state bit for identifying a run/stop state of the master controller;

means for transmitting the data frame from the master controller to the slave controller, wherein the data frame is interpreted by the slave controller.

17. The master controller of claim 16, wherein a processor generates the data frame.

18. The master controller of claim 17, wherein the processor is a Mitsubishi M16C.

19. The master controller of claim 16, wherein the data frame is transmitted through an EIA-485 port on to a data bus and the slave controller is operably connected to the data bus.

20. The master controller of claim 16, wherein the direction bit is set to 0 for identifying the source of the data frame as the master controller.

21. The master controller of claim 16, further comprising a means for receiving data from the slave controller in response to the direction bit of the control byte being set to 1.

22. The master controller of claim 16, wherein the data frame further comprises the data packet having a plurality of data words.

23. The master controller of claim 22, wherein the data packet comprises a first data word, a second data word, a third data word, and a fourth data word, wherein each data word comprises a first byte and a second byte.

24. The master controller of claim 16, wherein the data frame comprises a check sum byte comprising a two'"'"'s complement ADD check of the control byte and the data packet.

25. A method for transmitting a data frame from a master controller to a slave controller, the method comprising the steps of:

generating a data frame wherein the data frame comprises a control byte comprising a first address bit, a second address bit, and a third address bit for identifying a slave controller, a type bit following the first address bit, the second address bit, and the third address bit for identifying a data type in a data packet, a direction following the type bit for identifying a source of the data frame, a content bit following the direction bit for identifying whether the data packet comprises data, a state bit following the content bit for identifying the state of the master controller, and a run/stop bit following the state bit for identifying a run/stop state of the master controller; and

,

transmitting the data frame from the master controller to the slave controller, wherein the data frame is interpreted by the slave controller.

26. The method of claim 25, wherein the data frame is transmitted through an EIA-485 port on to a data bus and the slave controller is operably connected to the data bus.

27. The method of claim 25, wherein the direction bit is set to 0 for identifying the source of the data as the master controller.

28. The method of claim 25, further comprising a step of receiving data from a slave controller in response to the direction bit being set to 1.

29. The method of claim 25, wherein the data frame further comprises the data packet having a plurality of data words.

30. The method of claim 29 wherein the data packet comprises a first data word, a second data word, a third data word, and a fourth data word, wherein each data word comprise a first byte and a second byte.

31. The method of claim 25, wherein the data frame comprises a check sum byte comprising a two'"'"'s complement ADD check of the control byte and the data packet.

32. A slave controller for receiving a data frame from a master controller, the slave controller comprising:

means for receiving a data frame from a master controller wherein the data frame comprises a control byte comprising a first address bit, a second address bit, and a third address bit for identifying a slave controller, a type bit following the first address bit, the second address bit, and the third address bit for identifying a data type in a data packet, a direction following the type bit for identifying a source of the data frame, a content bit following the direction bit for identifying whether the data packet comprises data, a state bit following the content bit for identifying the state of the master controller, and a run/stop bit following the state bit for identifying a run/stop state of the master controller;

means for decoding the first address bit, the second address bit, the third address bit, and the type bit to confirm said data frame is addressed to said slave controller and said type bit corresponds to said slave controller configuration.

33. The slave controller of claim 32, wherein a processor receives the data frame.

34. The slave controller of claim 33, wherein the processor is a Mitsubishi M16C.

35. The slave controller of claim 32, wherein the data frame is received from a data bus through an EIA-485 port.

36. The slave controller of claim 32, further comprising a means for transmitting data from the slave controller to the master controller.

37. The slave controller of claim 32, wherein the data packet comprises a first data word, a second data word, a third data word, and a fourth data word, wherein each data word comprises a first byte and a second byte.

38. The slave controller of claim 32, further comprising a means for decoding the direction bit, the content bit, the state bit, and the run/stop bit.

39. The slave controller of claim 38, further comprising a means for storing the state bit in the slave controller.