Systems and methods for interconnection of multiple FPGA devices
First Claim
1. An ASIC array, comprising:
- three or more ASIC devices, each of said ASIC devices being a separate chip from the other of said three or more ASIC devices and having at least a first serial connection and a second serial connection;
wherein a first serial connection of a first one of said three or more ASIC devices is coupled to a first serial connection of a second one of said ASIC devices with no other serial connection therebetween to form a first serial data communication link;
wherein a second serial connection of said first one of said three or more ASIC devices is coupled to a first serial connection of a third one of said three or more other ASIC devices with no other serial connection therebetween to form a second serial data communication link; and
wherein a second serial connection of said second one of said three or more ASIC devices is coupled to a second serial connection of said third one of said three or more ASIC devices with no other serial connection therebetween to form a third serial data communication link;
wherein each of said first, second and third serial data communication links comprise duplex serial data communication links; and
wherein said three or more ASIC devices of said ASIC array are configured to bi-directionally transfer data packets across each of said first, second and third duplex serial data communication links such that one data packet is transferred in whole by a given one of said first, second and third duplex serial data communication links during transfer of said data packet across said given one of said first, second and third duplex serial data communication links.
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Accused Products
Abstract
Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.
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Citations
68 Claims
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1. An ASIC array, comprising:
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three or more ASIC devices, each of said ASIC devices being a separate chip from the other of said three or more ASIC devices and having at least a first serial connection and a second serial connection; wherein a first serial connection of a first one of said three or more ASIC devices is coupled to a first serial connection of a second one of said ASIC devices with no other serial connection therebetween to form a first serial data communication link; wherein a second serial connection of said first one of said three or more ASIC devices is coupled to a first serial connection of a third one of said three or more other ASIC devices with no other serial connection therebetween to form a second serial data communication link; and wherein a second serial connection of said second one of said three or more ASIC devices is coupled to a second serial connection of said third one of said three or more ASIC devices with no other serial connection therebetween to form a third serial data communication link; wherein each of said first, second and third serial data communication links comprise duplex serial data communication links; and wherein said three or more ASIC devices of said ASIC array are configured to bi-directionally transfer data packets across each of said first, second and third duplex serial data communication links such that one data packet is transferred in whole by a given one of said first, second and third duplex serial data communication links during transfer of said data packet across said given one of said first, second and third duplex serial data communication links. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. Signal processing circuitry comprising two or more ASIC devices, each one of said two or more ASIC devices being a separate chip from the other of said two or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, a reader interface of said packet router of each one of said two or more ASIC devices being coupled to a respective writer interface of each respective packet router of each of the other of said two or more ASIC devices by a separate respective duplex data communication link so as to form a direct serial interconnection between each two of said two or more ASIC devices;
- wherein each given one of said duplex serial data communication links is configured to transfer a data packet between two of said ASIC devices in a manner such that one data packet is transferred in whole by a given one of said duplex serial data communication links during said transfer of said data packet across said given one of said duplex serial data communication links and wherein;
said packet router of each respective one of said two or more ASIC devices is configured to process multiple simultaneous requests for transfer of data packets and to determine a destination of a given data packet from a routing code contained within a header of said given data packet and to transmit said given data packet across one of said duplex serial data communication links from at least one of said writer interfaces of said packet router of the same respective ASIC device to a reader interface of another one of said respective two or more ASIC devices based on said destination determined from said routing code contained within said header of said given data packet. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 43)
- wherein each given one of said duplex serial data communication links is configured to transfer a data packet between two of said ASIC devices in a manner such that one data packet is transferred in whole by a given one of said duplex serial data communication links during said transfer of said data packet across said given one of said duplex serial data communication links and wherein;
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34. A method of routing data packets between three or more ASIC devices of an ASIC array that each comprise a first serial connection and a second serial connection, said method comprising:
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transferring at least one data packet across a first serial data communication link formed between a first serial connection of a first one of said three or more ASIC devices and a first serial connection of a second one of said three or more ASIC devices with no other serial connection therebetween; transferring at least one data packet across a second serial data communication link formed between a second serial connection of said first one of said three or more ASIC devices and a first serial connection of a third one of said three or more other ASIC devices with no other serial connection therebetween; and transferring at least one data packet across a third serial data communication link formed between a second serial connection of said second one of said three or more ASIC devices and a second serial connection of said third one of said three or more ASIC devices with no other serial connection therebetween; wherein each of said first, second and third communication links comprise duplex data communication links;
wherein said method further comprises bi-directionally transferring data packets across each given one of said first, second and third duplex serial data communication links such that one data packet is transferred in whole by a given one of said duplex serial data communication links during said transfer of said data packet across said given one of said duplex serial data communication links; andwherein each of said three or more ASIC devices is a separate chip from the other of said three or more ASIC devices. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 44)
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45. A method of processing signals using signal processing circuitry comprising two or more ASIC devices, each one of said two or more ASIC devices being a separate chip from the other of said two or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, and said method comprising transferring at least one data packet from each said packet router of each one of said two or more ASIC devices to each respective packet router of each of the other of said two or more ASIC devices by a separate respective duplex data communication link that forms a direct serial interconnection between each two of said two or more ASIC devices, said separate respective duplex data communication link being coupled between a reader interface of said packet router of one of said two or more ASIC devices and a respective writer interface of another of said two or more ASIC devices and wherein said method further comprises:
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transferring data packets across each given one of said duplex data communication links such that one data packet is transferred in whole by a given one of said duplex data communication links during said transfer of said data packet across said given one of said duplex data communication links, and processing multiple simultaneous requests for transfer of data packets and determining a destination of a given data packet in a packet router of one of said two or more ASIC devices from a routing code contained within a header of said given data packet and transmitting said given data packet across one of said duplex serial data communication links from at least one writer interface of said packet router of the same respective ASIC device to a reader interface of another one of said respective two or more ASIC devices based on said destination determined from said routing code contained within said header of said given data packet. - View Dependent Claims (46, 47, 48, 58, 59)
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49. Signal processing circuitry comprising three or more ASIC devices, each one of said three or more ASIC devices being a separate chip from the other of said three or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router of each one of said three or more ASIC devices having multiple reader interfaces and multiple writer interfaces, said packet router of each one of said three or more ASIC devices also being coupled to each respective packet router of each one of the other of said three or more ASIC devices by a separate respective duplex data communication link so as to form a direct interconnection between each two of said three or more ASIC devices;
- and wherein said packet router of each respective one of said three or more ASIC devices is configured to process multiple simultaneous requests for transfer of data packets and to determine a destination of a given data packet from a routing code contained within a header of said given data packet and to transmit said given data packet across one of said duplex data communication links from at least one of said writer interfaces of said packet router of the same respective ASIC device to a reader interface of another one of said respective three or more ASIC devices based on said destination determined from said routing code contained within said header of said given data packet.
- View Dependent Claims (50, 51, 52, 53, 54, 55)
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56. Signal processing circuitry comprising three or more ASIC devices coupled together by one or more duplex serial data communication links and being configured so that any given one of said three or more ASIC devices may bi-directionally communicate across a duplex serial data communication link with any given other one of said three or more ASIC devices, said duplex serial data communication link comprising no more than two serial connections;
- wherein each of said three or more ASIC devices comprises a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, a reader interface of said packet router of each one of said three or more ASIC devices being coupled to a respective writer interface of each respective packet router of each of the other of said three or more ASIC devices by a separate respective duplex serial data communication link so as to form a direct serial interconnection between each two of said three or more ASIC devices; and
wherein each given one of said duplex serial data communication links is configured to transfer a data packet between two of said ASIC devices in a manner such that one data packet is transferred in whole by a given one of said duplex serial data communication links during said transfer of said data packet across said given one of said duplex serial data communication links; and
wherein each of said three or more ASIC devices is a separate chip from the other of said three or more ASIC devices.
- wherein each of said three or more ASIC devices comprises a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, a reader interface of said packet router of each one of said three or more ASIC devices being coupled to a respective writer interface of each respective packet router of each of the other of said three or more ASIC devices by a separate respective duplex serial data communication link so as to form a direct serial interconnection between each two of said three or more ASIC devices; and
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57. A method of processing signals using three or more ASIC devices, said method comprising bi-directionally communicating signals across a duplex serial data communication link from any given one of said three or more ASIC devices to any given other one of said three or more ASIC devices, said duplex serial data communication link comprising no more than two serial connections;
- wherein said method further comprises transferring a data packet across a given duplex serial data communication link between two of said three or more ASIC devices in a manner such that one data packet is transferred in whole by a given one of said duplex serial data communication links during said transfer of said data packet across said given one of said duplex serial data communication links;
wherein each of said three or more ASIC devices is a separate chip from the other of said three or more ASIC devices; and
wherein each of said three or more ASIC devices comprises a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, a reader interface of said packet router of each one of said three or more ASIC devices being coupled to a respective writer interface of each respective packet router of each of the other of said three or more ASIC devices by a separate respective duplex serial data communication link so as to form a direct serial interconnection between each two of said three or more ASIC devices.
- wherein said method further comprises transferring a data packet across a given duplex serial data communication link between two of said three or more ASIC devices in a manner such that one data packet is transferred in whole by a given one of said duplex serial data communication links during said transfer of said data packet across said given one of said duplex serial data communication links;
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60. A method of processing signals using signal processing circuitry comprising three or more ASIC devices, each one of said three or more ASIC devices being a separate chip from the other of said three or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router having multiple reader interfaces configured as packet sources and multiple writer interfaces configured as packet destinations, and said method comprising:
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transferring at least one data packet from each said packet router of each one of said three or more ASIC devices to each respective packet router of each of the other of said three or more ASIC devices by a separate respective duplex data communication link that forms a direct interconnection between each two of said three or more ASIC devices, each of said separate respective duplex data communication links being coupled between a reader interface of said packet router of one of said three or more ASIC devices and a respective writer interface of another of said three or more ASIC devices; and processing multiple simultaneous requests for transfer of data packets and determining a destination of a given data packet in a packet router of one of said three or more ASIC devices from a routing code contained within a header of said given data packet and transmitting said given data packet across one of said duplex data communication links from at least one writer interface of said packet router of the same respective ASIC device to a reader interface of another one of said respective three or more ASIC devices based on said destination determined from said routing code contained within said header of said given data packet. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68)
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Specification