System and method for code and data security in a semiconductor device

• US 7,444,476 B2
• Filed: 05/29/2002
• Issued: 10/28/2008
• Est. Priority Date: 07/24/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Foley, David P., Gnanasabapathy, Thiru
• Primary Examiner(s): Smithers; Matthew
• Assistant Examiner(s): Fields; Courtney D
• Application Number:
  US10/157,552
• Publication Number:
  US 20030023871A1
• Time in Patent Office: 2,344 Days
• Field of Search: 726/2, 726/5, 726/17, 726/27, 726/34, 713/186, 711/141, 711/143, 711/144
• US Class Current: 711/141
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/82 Protecting input, output or interconnection devices

Abstract

A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the device. A password for providing full communication in the data path is stored in a defined location in the memory. Upon reading the memory location, the password is provided to a code security module. The password provided to the code security module is compared to a data string provided by the user. If the password and the data string match, the password data path is open for communication between the memory and the processor core. If the password and data string do not match, the password data path is closed to communication between the memory and the processor core.

Claims

1. A method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device, comprising the steps of:

performing a read operation to a first memory location;

placing the content of the first memory location on a data bus coupled between the semiconductor device and the local memory while preventing the processor core from accessing the content of the first memory location from the data bus;

comparing the content of the first memory location to the content of a second memory location;

and selectively permitting or preventing the processor core to receive data from the local memory responsive to the comparing step.

2. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, wherein the step of performing a read operation to a first memory location comprises the step of reading a predefined memory location having preexisting password content.

3. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, further comprising the step of writing the content of the first memory location to a password register;

and

wherein the step of comparing the content of the first memory location to the content of the second memory location comprises the step of comparing the content of the password register to the content of the second memory location.

4. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, further comprising the step of writing the content of the first memory location to a password register;

and

wherein the step of comparing the content of the first memory location to the content of the second memory location comprises the step of comparing the content of the password register to the content of a key register.

5. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, wherein the selectively permitting step comprises the step of receiving at a memory buffer a signal indicative of the comparison of the content of the first memory location to the content of the second memory location.

6. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, further comprising the step of writing the content of the first memory location to a password register;

and

wherein the step of comparing the content of the first memory location to the content of the second memory location comprises the step of comparing the content of the password register to the content of a key register;

wherein the selectively permitting step comprises the step of receiving at a memory buffer a signal indicative of the comparison of the content of the password register to the content of the key register.

7. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, further comprising the step of permitting the processor core to receive data from the local memory regardless of the content of the second memory location if the content of the first memory location includes predefined default content.

8. The method for controlling access by the processor core of a semiconductor device to the local memory of the semiconductor device of claim 1, further comprising the step of permitting the processor core to receive data from the local memory regardless of the content of the second memory location if the content of the first memory location includes all ones.

9. A semiconductor device, comprising

a processor core;

memory;

a memory buffer positioned between the processor core and memory; and

wherein the memory buffer selectively allows or prevents data to pass between the memory and the processor core responsive to a comparison of a first set of data to a second set of data.

10. The semiconductor device of claim 9, wherein the first set of data comprises a first set of password data stored in memory.

11. The semiconductor device of claim 9,

wherein the first set of data comprises a first set of password data stored in memory;

wherein the second set of data comprises a second set of password data; and

wherein the memory buffer allows data to pass from memory to the processor core if the first set of password data is identical to the second set of password data.

12. The semiconductor device of claim 9,

wherein the first set of data comprises a first set of password data stored in memory;

wherein the second set of data comprises a second set of password data; and

wherein the memory buffer blocks the passage of data from memory to the processor core if the first set of password data is not identical to the second set of password data.

13. The semiconductor device of claim 9,

wherein the first set of data comprises a first set of password data stored in memory;

wherein the second set of data comprises a second set of password data;

wherein the memory buffer blocks the passage of data from memory to the processor core if the first set of password data is not identical to the second set of password data; and

wherein access to other components of the semiconductor device is permitted despite the blockage of the passage of data from the memory to the processor core.

14. The semiconductor device of claim 9, wherein at least one other component of the semiconductor device is placed opposite the processor core such that the memory buffer is positioned between the processor core and the other component of the semiconductor device, such that the memory buffer allows data to pass between the memory and the other component of the semiconductor device following a comparison of a first set of data to a second set of data.

15. A semiconductor device, comprising

a processor core;

memory;

security logic;

a memory buffer positioned between the processor core and memory; and

wherein the memory buffer selectively allows or prevents data to pass between the memory and processor core responsive to a signal received from security logic; and

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data.

16. The semiconductor device of claim 15,

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data stored in the memory;

and

wherein the password data is passed to the security logic following a read of the addresses of the password data in the memory.

17. The semiconductor device of claim 15,

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data stored in the memory;

wherein the password data is passed to the security logic following a read of the addresses of the password data in the memory; and

wherein the security logic generates the signal to the memory buffer indicating that the memory buffer should allow data to pass between the memory and the processor core if the password data includes predefined content.

18. The semiconductor device of claim 15,

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data stored in the memory;

wherein the password data is passed to the security logic following a read of the addresses of the password data in the memory; and

wherein the security logic generates the signal to the memory buffer indicating that the memory buffer should allow data to pass between the memory and the processor core if the password data includes all ones.

19. The semiconductor device of claim 15,

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data stored in the memory;

wherein the password data is passed to the security logic following a read of the addresses of the password data in the memory; and

wherein the security logic generates the signal to the memory buffer indicating that the memory buffer should allow data to pass between the memory and the processor core if the password data is identical to a second set of password data.

20. The semiconductor device of claim 15,

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data stored in the memory;

wherein the password data is passed to the security logic following a read of the addresses of the password data in the memory; and

wherein the security logic generates the signal to the memory buffer indicating that the memory buffer should not allow data to pass between the memory and the processor core if the password data is not identical to a second set of password data.

21. The semiconductor device of claim 15,

wherein the security logic generates the signal to the memory buffer on the basis of the content of password data stored in the memory;

wherein the password data is passed to the security logic following a read of the addresses of the password data in the memory;

wherein the security logic generates the signal to the memory buffer indicating that the memory buffer should not allow data to pass between the memory and the processor core if the password data is not identical to a second set of password data; and

wherein access to other components of the semiconductor device is permitted.

22. A semiconductor device of claim 15, further comprising,

a semiconductor device component coupled to the memory such that the memory buffer is positioned between the semiconductor device component and the processor core;

and

wherein the memory buffer allows data to pass between the semiconductor device component and processor on the basis of a signal received from security logic.

23. A method for securing a semiconductor device to prevent access to data on a local memory of the semiconductor device, comprising the steps of:

executing a read operation in the processor core of the device, the read operation directed to a predefined location in the memory housing a first set of password data;

copying the first set of password data to a first password register;

comparing the first set of password data of the first password register to a second set of password data; and

transmitting a data pass signal to a memory buffer between the processor core and the memory if the first set of password data is identical to the second set of password data.

24. The method for securing a semiconductor device to prevent access to data on a local memory of the semiconductor device of claim 23, wherein the first set of password data and the second set of password data are at least 56 bits.