Performance conserving method for reducing power consumption in a server system

• US 7,444,526 B2
• Filed: 06/16/2005
• Issued: 10/28/2008
• Est. Priority Date: 06/16/2005
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Rajamani, Karthick, Keller, Thomas Walter Jr., Felter, Wesley Michael, Rusu, Cosmin
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US11/154,160
• Publication Number:
  US 20060288241A1
• Time in Patent Office: 1,230 Days
• Field of Search: 713/300, 713/320, 713/322, 713/324
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component'"'"'s activity exceeds the component'"'"'s corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.

Claims

1. A method for managing power in a data processing system having at least one processor component and a memory component, comprising:

determining a power budget for the system;

determining a predicted level of activity for the processor and memory components;

based on said predicted level of activity, allocating a corresponding portion of the power budget to the processor and memory component, wherein allocating the portion of the power budget includes allocating each component its corresponding standby power and a pro rata share of the system power available for dynamic powering based on the expected levels of activity;

determining an activity limit for each processor and memory component based on the corresponding allocated portion of the power budget; and

monitoring the activity of the processor and memory components and, responsive to determining activity in excess of a component'"'"'s corresponding activity limit, constraining the activity of the component.

2. A method for managing power in a data processing system having at least one processor component and a memory component, comprising:

determining a power budget for the system;

determining a predicted level of activity for the processor and memory components;

based on said predicted level of activity, allocating a corresponding portion of the power budget to the processor and memory component;

determining an activity limit for each processor and memory component based on the corresponding allocated portion of the power budget; and

monitoring the activity of the processor and memory components wherein monitoring an activity limit includes monitoring a processor performance monitor configured to count the number of instructions dispatched during a timing interval, and, responsive to determining activity in excess of a component'"'"'s corresponding activity limit, constraining the activity of the component, wherein constraining activity comprises preventing the processor from dispatching additional instructions or constraining the rate of dispatching instructions until a current timing interval expires.