Generation of memory test patterns for DLL calibration

• US 7,444,559 B2
• Filed: 01/28/2004
• Issued: 10/28/2008
• Est. Priority Date: 01/28/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Greeff, Roy E., Swanson, Travis E.
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US10/766,386
• Publication Number:
  US 20050166110A1
• Time in Patent Office: 1,735 Days
• Field of Search: 714/738, 714/712, 714/700, 714/707, 714/731, 714735-736, 714/744, 714/775, 714/798, 714718-719, 714/819, 365/200, 365/201, 365/233, 365/193, 365/194, 327/156
• US Class Current: 714/718
• CPC Class Codes: G01R 31/318328 for delay tests

Abstract

A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

Claims

1. A method of operating a processor connected to a memory through a bus having a plurality of bit lines, said method comprising:

selecting a first group of bit lines from said bus to carry a first plurality of data patterns;

selecting at least one of the remaining bit lines from said bus not within said first group to carry a second data pattern;

transmitting one or more of said first plurality of data patterns on said first group of bit lines in said bus;

transmitting said second data pattern on said at least one of the remaining bit lines;

performing data write/read operations at a data storage location in said memory using said bus and said one or more of said first plurality of data patterns and said second data pattern; and

adjusting a delay based on an accuracy of data read compared to data written in said data write/read operations.

2. The method of claim 1, wherein said performing includes:

performing reading of data as part of said data write/read operations in conjunction with a strobe signal received from a delay locked loop.

3. The method of claim 2, further comprising:

configuring said delay locked loop to provide said delay to said strobe signal such that said strobe signal is centered in the middle of data signals.

4. The method of claim 1, wherein said first plurality of data patterns contains said second data pattern.

5. The method of claim 1, further comprising:

transmitting a different data pattern of said first plurality of data patterns; and

repeating said transmitting of said second data pattern and said performing data write/read operations.

6. The method of claim 5, further comprising shifting a data pattern of said first plurality of data patterns by at least one bit to generate said different data pattern of said first plurality of data patterns.

7. The method of claim 1, wherein each data pattern of said first plurality of data patterns is concurrently transmitted with said second data pattern.

8. A system comprising:

a memory chip including a plurality of storage locations to store data;

a bus having a plurality of bit lines; and

a processor connected to said memory chip via said bus and in communication therewith through said bus, wherein said processor is configured to perform the following;

select a first group of bit lines from said bus to carry a first plurality of data patterns;

select at least one of the remaining bit lines from said bus not within said first group to carry a second plurality of data patterns;

transmit one or more of said first plurality of data patterns on said first group of bit lines,

transmit one or more of said second plurality of data patterns on said at least one of the remaining bit lines;

perform data write/read operations at one of said plurality of storage locations using said bus and said one or more of said first plurality of data patterns and said one or more of said second plurality of data patterns; and

adjust a delay based on an accuracy of data read compared to data written in said data write/read operations.

9. The system of claim 8, wherein said processor includes a delay locked loop circuit configured to provide a delayed strobe signal during reading of data as part of said data write/read operations.

10. The system of claim 8, wherein the number of bit lines in said plurality of bit lines is 2^N, where N≧

1.

11. The system of claim 8, wherein said processor is configured to transmit said one or more of said first plurality of data patterns and said one or more of said second plurality of data patterns concurrently.

12. The system of claim 8, wherein said processor includes:

a first linear feedback shift register configured to generate said first plurality of data patterns; and

a second linear feedback shift register configured to generate said second plurality of data patterns.

13. The system of claim 8, wherein said processor further includes a decode circuit having a plurality of output lines, wherein each output line is configured to be connected to one of said plurality of bit lines so as to allow transmission of said first and said second plurality of bit patterns on respective bit lines.

14. The system of claim 8, wherein said processor is further configured to shift said first plurality of data patterns by at least one bit from said second plurality of data patterns.

15. The system of claim 8, wherein said processor is further configured to perform transmission of said first plurality of data patterns and said second plurality of data patterns for each bit line in said plurality of bit lines.

16. A system comprising:

a memory chip including a plurality of storage locations to store data;

a bus having a plurality of bit lines; and

a processor connected to said memory chip via said bus and in communication therewith through said bus, wherein said processor is configured to perform the following;

select a first group of bit lines from said bus to carry a first plurality of data patterns;

select at least one of the remaining bit lines from said bus not within said first group to carry a second data pattern;

transmit one or more of said first plurality of data patterns on said first group of bit lines;

transmit said second data pattern on said at least one of the remaining bit lines; and

perform data write/read operations at one of said plurality of storage locations using said bus and said one or more of said first plurality of data patterns and said second data pattern ; and

adjust a delay applied to a strobe signal based on an accuracy of data read compared to data written in said data write/read operations.

17. The system of claim 16, wherein said processor is further configured to store said first plurality of data patterns and said second data pattern.

18. The system of claim 16, wherein said processor is further configured to transmit each data pattern of said first plurality of data patterns concurrently with said second data pattern.

19. A method of operating a processor connected to a memory through a bus having a plurality of bit lines, said method comprising:

selecting a first group of bit lines from said bus to carry a first plurality of data patterns;

selecting at least one of the remaining bit lines from said bus not within said first group to carry a second plurality of data patterns;

transmitting one or more of said first plurality of data patterns on said first group of bit lines,

transmitting one or more of said second plurality of data patterns on said at least one of the remaining bit lines;

performing data write/read operations at a data storage location in said memory using said bus and said one or more of said first plurality of data patterns and said one or more of said second plurality of data patterns; and

adjusting a delay based on an accuracy of data read compared to data written in said data write/read operations.

20. The method of claim 19, wherein said performing includes:

performing reading of data as part of said data write/read operations in conjunction with a strobe signal received from a delay locked loop.

21. The method of claim 20, further comprising:

configuring said delay locked loop to provide said delay to said strobe signal such that said strobe signal is centered in the middle of data signals.

22. The method of claim 19, wherein each of said one or more of said first plurality of data patterns is concurrently transmitted with one of said one or more of said second plurality of data patterns.