Trusted computing platform

• US 7,444,601 B2
• Filed: 10/12/2005
• Issued: 10/28/2008
• Est. Priority Date: 02/15/1999
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Proudler, Graeme John, Chen, Liqun, Chan, David, Gupta, Dipankar, Balacheff, Boris, Pearson, Siani Lynne, Van Wilder, Bruno Edgard
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/249,820
• Publication Number:
  US 20060031790A1
• Time in Patent Office: 1,112 Days
• Field of Search: 716/1, 716/16, 716/17, 716/18
• US Class Current: 713/150
• CPC Class Codes: G06F 21/34 involving the use of external additional devices, e.g. dongles or smart cards
• CPC Class Codes: G06F 21/445 by mutual authentication, e.g. between devices or programs
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 2211/009 Trust
• CPC Class Codes: G06F 2221/2103 Challenge-response

Abstract

In a computing platform, a trusted hardware device (24) is added to the motherboard (20). The trusted hardware device (24) is configured to acquire an integrity metric, for example a hash of the BIOS memory (29), of the computing platform. The trusted hardware device (24) is tamper-resistant, difficult to forge and inaccessible to other functions of the platform. The hash can be used to convince users that that the operation of the platform (hardware or software) has not been subverted in some way, and is safe to interact with in local or remote applications.

In more detail, the main processing unit (21) of the computing platform is directed to address the trusted hardware device (24), in advance of the BIOS memory, after release from ‘reset’. The trusted hardware device (24) is configured to receive memory read signals from the main processing unit (21) and, in response, return instructions, in the native language of the main processing unit (21), that instruct the main processing unit to establish the hash and return the value to be stored by the trusted hardware device (24). Since the hash is calculated in advance of any other system operations, this is a relatively strong method of verifying the integrity of the system. Once the hash has been returned, the final instruction calls the BIOS program and the system boot procedure continues as normal.

Whenever a user wishes to interact with the computing platform, he first requests the integrity metric, which he compares with an authentic integrity metric that was measured by a trusted party. If the metrics are the same, the platform is verified and interactions can continue. Otherwise, interaction halts on the basis that the operation of the platform may have been subverted.

Claims

1. Computing apparatus comprising, mounted on an assembly, a main processor, a main memory and a trusted device, wherein the trusted device itself comprises a trusted device processor and a trusted device memory, whereby the trusted device processor is arranged to acquire a true value of an integrity metric of the computing apparatus and the trusted device memory contains a certificate signed by a trusted third party, whereby the trusted device is adapted to report the true value of the integrity metric together with the certificate.

2. Computing apparatus according to claim 1, wherein the trusted device has stored in trusted device memory a unique identity of the trusted device and a secret.

3. Computing apparatus according to claim 2, wherein the secret comprises a private encryption key.

4. Computing apparatus according to claim 3, wherein the trusted device memory also contains a respective public encryption key that has been signed by a trusted party.

5. Computing apparatus according to claim 3, wherein the trusted device processor has access to an encryption function and whereby the trusted device is arranged to generate a response to a received challenge, the response comprising the true value of the integrity metric signed by the encryption function using the private asymmetric encryption key.

6. Computing apparatus according to claim 1, wherein the certificate contains a reference value of the integrity metric.

7. Computing apparatus according to claim 1, wherein the certificate contains a public key of the trusted device.

8. A trusted device for use as a functional component in a computing apparatus, the trusted device being adapted for mounting on an assembly of the computing apparatus and comprising:

an interface for communication with other functional components of the computing apparatus,

a trusted device processor, and

a trusted device memory storing a certificate signed by a trusted third party;

the trusted device being adapted to acquire a true value of an integrity metric of the computing apparatus and to report this true value together with the certificate.

9. A trusted device according to claim 8, wherein the certificate contains a reference value of the integrity metric.

10. A trusted device according to claim 8, wherein the certificate contains a public key of the trusted device.