Load balanced interrupt handling in an embedded symmetric multiprocessor system

• US 7,444,639 B2
• Filed: 09/27/2002
• Issued: 10/28/2008
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jahnke, Steven R.
• Primary Examiner(s): Ho; Andy
• Application Number:
  US10/256,697
• Publication Number:
  US 20030120702A1
• Time in Patent Office: 2,223 Days
• Field of Search: 710/260, 719/318, 718/105
• US Class Current: 718/105
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/505 considering the load

Abstract

In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the interrupt and then passes information to the central processing unit scheduling software. This software will in turn determine which central processing unit can best handle the interrupt. Because the scheduling software is able to determine which central processing unit handles the interrupt process, it can maintain central processing unit load balancing resulting in better system performance.

Claims

1. A data processing method employing a plurality of central processing units, said method comprising the steps of:

scheduling tasks among said plurality of central processing units;

receiving an external interrupt on a predetermined central processing unit;

determining current loading of each of said plurality of central processing units; and

scheduling interrupt tasks among said plurality of central processing units based upon said current loading of each of said plurality of central processing units to dynamically balance loading among said plurality of central processing units including dividing servicing a current interrupt into a plurality of tasks and distributing different ones of said plurality of tasks of said current interrupt to different ones of said plurality of central processing units.

2. A data processing method employing a plurality of central processing units, said method comprising the steps of:

scheduling tasks among said plurality of central processing units;

receiving an external interrupt on a predetermined central processing unit including mapping interrupt sources to corresponding central processing units;

determining current loading of each of said plurality of central processing units; and

scheduling interrupt tasks among said plurality of central processing units based upon said current loading of each of said plurality of central processing units to dynamically balance loading among said plurality of central processing units including upon receipt of said external interrupt one of said corresponding central processing units passing information of said external interrupt to interrupt scheduling decision software to schedule interrupt tasks of said external interrupt to one or more of said plurality of central processing units.

3. The data processing method of claim 2, wherein:

said step of scheduling tasks among said plurality of central processing units including dividing said interrupt scheduling decision software into a plurality of tasks and distributing different ones of said plurality of tasks of said interrupt scheduling decision software to different ones of said plurality of central processing units.

4. The data processing method of claim 2, wherein:

said step of mapping interrupt sources to corresponding central processing units includes programming control registers to determine which interrupt source is mapped to which corresponding central processing unit.