Context controller having context-specific event selection mechanism and processor employing the same

• US 7,444,641 B1
• Filed: 12/17/1998
• Issued: 10/28/2008
• Est. Priority Date: 03/10/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Fischer, Michael A., Hardell, Wesley D., Diepstraten, Wilhelmus J. M.
• Primary Examiner(s): Donaghue; Larry D
• Application Number:
  US09/213,984
• Time in Patent Office: 3,603 Days
• Field of Search: 718104-106, 712/228, 712/229
• US Class Current: 718/107
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences of predetermined events and (2) an event acknowledger, associated with the event recorder, that acknowledges ones of the events based on an identity of a currently-active context.

Claims

1. A context controller for managing multitasking in a processor, comprising:

an event recorder that records occurrences of predetermined events; and

an event acknowledger, associated with said event recorder, that only acknowledges ones of said events having a same context as a currently-active context of code executing on said processor.

2. The context controller as recited in claim 1 wherein said contexts are defined and activation events of said contexts are predetermined, wherein an acknowledgment from said event acknowledger is used to clear said activation events.

3. The context controller as recited in claim 2 further comprising an event masker, associated with said event recorder, said event acknowledger and each context executing on said processor, that masks others of said events as a function of said each context and only allows activation of said contexts based on said activation events being identified by said event masker.

4. The context controller as recited in claim 1 further comprising:

a foreground task controller that activates contexts corresponding to foreground tasks based on priority and in response to said events; and

a background task controller that cyclicly activates contexts corresponding to said background tasks subject to activation of said contexts corresponding to said foreground tasks.

5. The context controller as recited in claim 1 further comprising a background task controller that activates contexts corresponding to background tasks based on numbers of instructions executed by each of said background tasks, wherein said each of said background tasks accomplishes an equal amount of work before a cycle of background processing repeats.

6. The context controller as recited in claim 1 wherein said context controller places said processor in an idle state responsive to all foreground and background tasks being inactive.

7. The context controller as recited in claim 1 further comprising a foreground task controller adapted to activate a context corresponding to a particular foreground task by vectoring to a software-selectable memory location.

8. A method of managing multitasking in a processor, comprising the steps of:

recording occurrences of predetermined events;

determining a currently-active context of code executing on said processor; and

acklowledging only ones of said events having a same context as said currently-active context.

9. The method as recited in claim 8 further comprising the step of masking others of said events as a function of each context executing on said processor.

10. The method as recited in claim 8 wherein said step of recording comprises the step of changing a state of at least one flip-flop within said context controller.

11. The method as recited in claim 8 further comprising the steps of:

activating contexts corresponding to foreground tasks based on priority and in response to said events; and

cyclicly activating contexts corresponding to said background tasks subject to activation of said contexts corresponding to said foreground tasks.

12. The method as recited in claim 8 further comprising the step of activating contexts corresponding to background tasks based on numbers of instructions executed by each of said background tasks, wherein said each of said background tasks accomplishes an equal amount of work before a cycle of background processing repeats.

13. The method as recited in claim 8 further comprising the step of placing said processor in an idle state in response to all foreground and background tasks being inactive.

14. The method as recited in claim 8 further comprising the step of activating a context corresponding to a particular foreground task by vectoring to a software-selectable memory location.

15. A processor, comprising:

an instruction decoder that decodes instructions received into said processor and corresponding to a plurality of tasks;

a plurality of register sets, corresponding to said plurality of tasks, that contain operands to be manipulated;

an execution core, coupled to said instruction decoder and said plurality of register sets, that executes instructions corresponding to an active one of said plurality of tasks to manipulate ones of said operands; and

a context controller for managing multitasking in said processor, including;

an event recorder that records occurrences of predetermined events; and

an event acknowledger, associated with said event recorder, that only acknowledges ones of said events having a same context as a currently-active context of code executing on said processor.

16. The processor as recited in claim 15 wherein said context controller further includes an event masker, associated with said event recorder, said event acknowledger and each context executing on said processor, that masks others of said events as a function of said each context.

17. The processor as recited in claim 15 wherein said event recorder is embodied in at least one flip-flop within said context controller.

18. The processor as recited in claim 15 wherein said context controller further includes:

a foreground task controller that activates contexts corresponding to foreground tasks based on priority and in response to said events; and

a background task controller that cyclicly activates contexts corresponding to said background tasks subject to activation of said contexts corresponding to said foreground tasks.

19. The processor as recited in claim 15 wherein said context controller further includes a background task controller that activates contexts corresponding to background tasks based on numbers of instructions executed by each of said background tasks, wherein said each of said background tasks accomplishes an equal amount of work before a cycle of background processing repeats.

20. The processor as recited in claim 15 wherein said context controller places said processor in an idle state responsive to all foreground and background tasks being inactive.

21. The processor as recited in claim 15 wherein said context controller further includes a foreground task controller adapted to activate a context corresponding to a particular foreground task by vectoring to a software-selectable memory location.

22. The processor as recited in claim 15 wherein said processor forms a portion of a general-purpose computer.