Process for manufacturing an integrated circuit system

• US 7,444,735 B2
• Filed: 06/02/2005
• Issued: 11/04/2008
• Est. Priority Date: 06/15/2004
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Tan, Victor, Cheong, Kai Keong, Bay, Stanley, Lo, Marvin, Yeo, David, Yong, Anthony
• Primary Examiner(s): Vo; Peter DungBa
• Assistant Examiner(s): NGUYEN, TAI V
• Application Number:
  US10/908,973
• Publication Number:
  US 20050276028A1
• Time in Patent Office: 1,251 Days
• Field of Search: 296/00, 298/40, 298/41, 298/25, 298/30, 298/31, 298/27, 298/32, 296/01, 298/46, 298/47, 343/700.MS, 343/700.R, 343/767, 343/770, 343/771, 361/760, 361/783, 361/782, 438/200
• US Class Current: 29/600
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: G08B 13/2417 having a radio frequency identification chip
• CPC Class Codes: G08B 13/2437 Tag layered structure, processes for making layered tags
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making
• CPC Class Codes: Y10T 29/49018 with other electrical component
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A system for manufacturing an integrated circuit system having a substrate with a integrated circuit device. A first pad is formed on the substrate and connected to the integrated circuit device. A first dielectric layer is formed over the substrate and the first pad, with the first dielectric layer having an opening provided therein exposing the first pad. An upper redistribution layer is formed over the first dielectric layer. A portion of the upper redistribution layer is formed into an antenna with the antenna connected to the first pad. A second dielectric layer is formed over the first dielectric layer and over the antenna.

Claims

1. A process for manufacturing an integrated circuit process comprising:

forming a substrate having an integrated circuit device;

forming a first pad on the substrate connected to the integrated circuit device;

forming a first dielectric layer over the substrate and the first pad, the first dielectric layer having an opening provided therein exposing the first pad;

forming an upper redistribution layer over the first dielectric layer;

forming at least a portion of the upper redistribution layer into an antenna having two ends, the antenna connected to the first pad;

forming a plurality of pillars on the first pad. the plurality of pillars connected to one end of the antenna;

forming a second pillar connected to the other end of the antenna at the same time as forming the plurality of pillars on the first pad;

forming a second pad connected to the second pillar; and

forming a second dielectric layer over the first dielectric layer and over the antenna.

2. The process as claimed in claim 1 further comprising forming a lower redistribution layer on the first pad and connected to the antenna.

3. The process as claimed in claim 1 further comprising forming a pillar on the first pad and over the first dielectric layer, the pillar connected to the antenna.

4. The process as claimed in claim 1 further comprising:

forming a first pillar on the first pad;

forming a third dielectric layer over the first pillar, the third dielectric layer having an opening provided therein exposing the first pillar; and

forming a second pillar on the pad in the opening in the third dielectric layer, the second pillar in contact with the antenna.

5. A process for manufacturing an integrated circuit process comprising:

forming a substrate having a radio frequency identification integrated circuit device;

forming a first pad on the substrate connected to the radio frequency identification integrated circuit device;

forming a first dielectric layer over the substrate and the first pad, the first dielectric layer having an opening provided therein exposing the first pad;

forming an upper redistribution layer over the first dielectric layer;

forming at least a portion of the upper redistribution layer into an antenna having two ends, the antenna connected to the first pad;

forming a plurality of pillars on the first pad, the plurality of pillars connected to one end of the antenna;

forming a second pillar connected to the other end of the antenna at the same time as forming the plurality of pillars on the first pad;

forming a second pad connected to the second pillar; and

forming a second dielectric layer over the first dielectric layer and over the antenna.

6. The system as claimed in claim 5 further comprising forming a lower redistribution layer on the first pad and connected to the antenna.

7. The system as claimed in claim 5 further comprising forming a pillar on the first pad and over the first dielectric layer, the pillar connected to the antenna.

8. The system as claimed in claim 5 further comprising:

forming a first pillar on the first pad;

forming a third dielectric layer over the first pillar, the third dielectric layer having an opening provided therein exposing the first pillar; and

forming a second pillar on the pad in the opening in the third dielectric layer, the second pillar in contact with the antenna.