Method for making a semiconductor device comprising a superlattice dielectric interface layer

• US 7,446,002 B2
• Filed: 05/25/2005
• Issued: 11/04/2008
• Est. Priority Date: 06/26/2003
• Status: Expired due to Term

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Dukovski, Ilija, Halilov, Samed, Hytha, Marek, Mears, Robert J., Huang, Xiangyang, Yiptong, Jean Augustin Chan Sow Fook, Stephenson, Robert John, Kreps, Scott A., Rao, Kalipatnam Vivek
• Primary Examiner(s): Graybill; David E
• Application Number:
  US11/136,747
• Publication Number:
  US 20060019454A1
• Time in Patent Office: 1,259 Days
• Field of Search: None
• US Class Current: 438/285
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.

Claims

1. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers adjacent a semiconductor substrate;

each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween;

forming a high-K dielectric layer adjacent the superlattice; and

forming an electrode layer adjacent the high-K dielectric layer and opposite the superlattice.

2. The method of claim 1 wherein the high-K dielectric layer has a dielectric constant of greater than about five.

3. The method of claim 1 wherein the high-K dielectric layer has a dielectric constant of greater than about ten.

4. The method of claim 1 wherein the high-K dielectric layer has a dielectric constant of greater than about twenty.

5. The method of claim 1 wherein the at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions is less than about five monolayers to thereby function as an energy band-modifying layer.

6. The method of claim 1 further comprising forming a channel region underlying the superlattice.

7. The method of claim 6 further comprising forming source and drain regions adjacent the channel region.

8. The method of claim 1 wherein the high-K dielectric layer comprises at least one of silicon oxide, zirconium oxide, and hafnium oxide.

9. The method of claim 1 wherein the base semiconductor comprises silicon.

10. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

11. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.

12. The method of claim 1 wherein the at least one non-semiconductor monolayer is a single monolayer thick.

13. The method of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

14. The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.

15. The method of claim 1 wherein opposing base semiconductor monolayers in adjacent groups of layers of the superlattice are chemically bound together.

16. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers adjacent a semiconductor substrate;

each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer comprising at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and at least some silicon atoms from opposing base silicon portions being chemically bound together with the chemical bonds traversing the at least one oxygen monolayer therebetween;

forming a high-K dielectric layer having a dielectric constant of greater than about five adjacent the superlattice; and

forming an electrode layer adjacent the dielectric layer and opposite the superlattice.

17. The method of claim 16 wherein the high-K dielectric layer has a dielectric constant of greater than about twenty.

18. The method of claim 16 wherein the at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions is less than about five monolayers to thereby function as an energy band-modifying layer.

19. The method of claim 16 further comprising forming a channel region underlying the superlattice.

20. The method of claim 19 further comprising forming source and drain regions adjacent the channel region.

21. The method of claim 16 wherein the high-K dielectric layer comprises at least one of silicon oxide, zirconium oxide, and hafnium oxide.