Methods and apparatus for RF shielding in vertically-integrated semiconductor devices

• US 7,446,017 B2
• Filed: 05/31/2006
• Issued: 11/04/2008
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Liu, Lianjun, Li, Li, Bowles, Philip H.
• Primary Examiner(s): Geyer; Scott B.
• Assistant Examiner(s): Lee; Cheung
• Application Number:
  US11/444,091
• Publication Number:
  US 20070281438A1
• Time in Patent Office: 888 Days
• Field of Search: 438/599, 257/E21.087, 257/E21.48
• US Class Current: 438/455
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e.g., the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.

Claims

1. A method for forming a stacked die semiconductor structure, the method comprising:

providing a first semiconductor substrate having a first device formed therein;

providing a second semiconductor substrate having a second device formed therein, the second semiconductor substrate having a first set of vias extending therethrough to a metallic bonding layer;

forming an interconnect on the first semiconductor substrate;

forming a dielectric layer on the first semiconductor substrate;

forming a second set of vias through the dielectric layer such that it contacts the interconnect and extends through the dielectric layer;

forming a patterned ground shield on the dielectric layer such that it contacts the second set of vias; and

directly bonding the bonding layer to the patterned ground shield.

2. The method of claim 1, wherein forming the patterned ground shield includes forming a metallic conductor.

3. The method of claim 1, wherein forming the patterned ground shield includes depositing a layer of aluminum having a thickness of between 0.5 microns and 3.0 microns.

4. The method of claim 1, wherein the bonding layer has a pattern substantially conforming to a pattern defined by the first set of vias.

5. The method of claim 4, wherein the second set of vias has a pattern substantially conforming to the pattern defined by the first set of vias.

6. The method of claim 4, wherein the bonding layer includes metallic regions having an area substantially the same as the area of the first set of vias extending through the first semiconductor substrate.