Post passivation interconnection schemes on top of IC chips
First Claim
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1. A method for fabricating a chip, comprising:
- providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said first internal circuit, and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process; and
forming a third interconnecting structure over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said forming said third interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
20 Claims
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1. A method for fabricating a chip, comprising:
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providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said first internal circuit, and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming a third interconnecting structure over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said forming said third interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for fabricating a chip, comprising:
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providing a silicon substrate, an internal circuit in or on said silicon substrate, and a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said internal circuit, and wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said internal circuit through said first interconnecting structure, and wherein said forming said second interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification