Post passivation interconnection schemes on top of IC chips

• US 7,446,035 B2
• Filed: 09/17/2007
• Issued: 11/04/2008
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Ghyka; Alexander G
• Application Number:
  US11/856,081
• Publication Number:
  US 20080045004A1
• Time in Patent Office: 414 Days
• Field of Search: 438/623, 438/637, 438/638
• US Class Current: 438/637
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A method for fabricating a chip, comprising:

providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said first internal circuit, and a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process; and

forming a third interconnecting structure over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure, and wherein said forming said third interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.

2. The method of claim 1, wherein said forming said first metal layer comprises a sputtering process.

3. The method of claim 1 further comprising providing a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure.

4. The method of claim 3 further comprising providing a fourth internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said fourth internal circuit, wherein said first and third internal circuits are connected to said fourth internal circuit through said first interconnecting structure, and wherein said fourth internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure.

5. The method of claim 3 further comprising providing a fourth internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said fourth internal circuit, wherein said second internal circuit is connected to said fourth internal circuit through said second interconnecting structure, and wherein said first and third internal circuits are connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said third interconnecting structure and said second interconnecting structure.

6. The method of claim 1, wherein said third interconnecting structure comprises a clock bus over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through said clock bus.

7. The method of claim 1, wherein said third interconnecting structure comprises a signal bus over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through said signal bus.

8. The method of claim 1, wherein said third interconnecting structure comprises a power bus over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through said power bus.

9. The method of claim 1, wherein said third interconnecting structure comprises a ground bus over said silicon substrate, wherein said first internal circuit is connected to said second internal circuit through said ground bus.

10. The method of claim 1 further comprising providing a dielectric layer over said silicon substrate, wherein said first and second interconnecting structures are in said dielectric layer, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, and wherein said forming said third interconnecting structure comprises said forming said third interconnecting structure further over said passivation layer.

11. The method of claim 10 further comprising providing a polymer layer over said passivation layer, wherein said third interconnecting structure is in said polymer layer.

12. The method of claim 11, wherein said polymer layer has a thickness greater than 2 micrometers.

13. The method of claim 1, wherein said third interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.

14. A method for fabricating a chip, comprising:

providing a silicon substrate, an internal circuit in or on said silicon substrate, and a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is connected to said internal circuit, and wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and

forming a second interconnecting structure over said silicon substrate, wherein said second interconnecting structure is connected to said internal circuit through said first interconnecting structure, and wherein said forming said second interconnecting structure comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.

15. The method of claim 14, wherein said forming said first metal layer comprises a sputtering process.

16. The method of claim 14 further comprising providing an ESD circuit in or on said silicon substrate, wherein said internal circuit is connected to said ESD circuit through, in sequence, said first interconnecting structure and said second interconnecting structure.

17. The method of claim 14 further comprising providing a driver, receiver or I/0 circuit in or on said silicon substrate, wherein said internal circuit is connected to said driver, receiver or I/O circuit through, in sequence, said first interconnecting structure and said second interconnecting structure.

18. The method of claim 14 further comprising providing a dielectric layer over said silicon substrate, wherein said first interconnecting structure is in said dielectric layer, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, and wherein said forming said second interconnecting structure comprises said forming said second interconnecting structure further over said passivation layer.

19. The method of claim 18 further comprising providing a polymer layer over said passivation layer, wherein said second interconnecting structure is in said polymer layer.

20. The method of claim 19, wherein said polymer layer has a thickness greater than 2 micrometers.