Method for sorting integrated circuit devices

• US 7,446,277 B2
• Filed: 03/06/2002
• Issued: 11/04/2008
• Est. Priority Date: 01/17/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J.
• Primary Examiner(s): HAGEMAN, MARK
• Application Number:
  US10/092,185
• Publication Number:
  US 20020088743A1
• Time in Patent Office: 2,435 Days
• Field of Search: 209/571, 209/573, 324/158.1, 324/759, 324/764, 324/765, 700/96, 700/108, 700/109, 700/121
• US Class Current: 209/573
• CPC Class Codes: B07C 5/3412 according to a code applied to the object which indicates a property of the object, e.g. quality class, contents or incorrect indication sorting according to size measured by light-responsive means B07C5/10; sorting according to optical properties B07C5/342; for packages B65D79/02; for information carriers G06K7/00
• CPC Class Codes: B07C 5/344 according to electric or electromagnetic properties sorting according to size measured electrically or electronically B07C5/08; material testing by magnetic means G01N24/00, G01N27/00, by electrical means G01N27/00; electrical measuring devices in general G01R; coin testing G07D5/00
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

Claims

1. A testing method for an integrated circuit of an integrated circuit device of a plurality of integrated circuit devices comprising:

establishing an enhanced reliability testing flag for an integrated circuit device resulting from fabrication errors and manufacturing deviations from a manufacturing process for an integrated circuit device of a plurality of integrated circuit devices;

storing an enhanced reliability testing flag in the integrated circuit device associated with a unique identification code of each integrated circuit device of the plurality of integrated circuit devices for indicating whether each integrated circuit device requires enhanced reliability testing;

automatically reading the unique identification code of each integrated circuit device of the plurality of integrated circuit devices when each integrated circuit device of the plurality of integrated circuit devices forms a portion of a wafer;

accessing the enhanced reliability testing flag stored for the unique identification code of each integrated circuit device of the plurality of integrated circuit devices;

sorting the plurality of integrated circuit devices in accordance with whether their enhanced reliability testing flag indicates they are in need of the enhanced reliability testing; and

performing the enhanced reliability testing for each integrated circuit device of the plurality of integrated circuit devices requiring the enhanced reliability testing.

2. A reliability testing method for an integrated circuit of an integrated circuit device of a plurality of integrated circuit devices comprising:

establishing an enhanced reliability testing flag for an integrated circuit device resulting from fabrication errors and manufacturing deviations from a manufacturing process for an integrated circuit device of a plurality of integrated circuit devices;

storing an enhanced reliability testing flag in the integrated circuit device associated with a unique identification code of each integrated circuit device of the plurality of integrated circuit devices for indicating whether each integrated circuit device requires further reliability testing;

automatically reading the unique identification code of each integrated circuit device of the plurality of integrated circuit devices;

accessing the enhanced reliability testing flag stored for each unique identification code of each integrated circuit device of the plurality of integrated circuit devices;

sorting the plurality of integrated circuit devices in accordance with whether their enhanced reliability testing flag indicates they are in need of the further reliability testing; and

performing the further reliability testing for each integrated circuit device of the plurality of integrated circuit devices requiring the further reliability testing.

3. A manufacturing method for an integrated circuit of an integrated circuit device of a plurality of integrated circuit devices comprising:

establishing an enhanced reliability testing flag for an integrated circuit device resulting from fabrication errors and manufacturing deviations from a manufacturing process for an integrated circuit device of a plurality of integrated circuit devices;

storing an enhanced reliability testing flag in the integrated circuit device associated with a unique identification code of each integrated circuit device of the plurality of integrated circuit devices for indicating whether each integrated circuit device requires further reliability testing;

automatically reading the unique identification code of each integrated circuit device of the plurality of integrated circuit devices;

accessing the enhanced reliability testing flag stored for each unique identification code of each integrated circuit device of the plurality of integrated circuit devices;

sorting the plurality of integrated circuit devices in accordance with whether their enhanced reliability testing flag indicates they are in need of the further reliability testing; and

performing the further reliability testing for each integrated circuit device of the pluratity of integrated circuit devices requiring the further reliability testing.