Fabricated layered capacitor for a digital-to-analog converter
First Claim
1. A capacitor device array comprising:
- an array of at least two capacitor devices arranged in columns and rows,wherein each capacitor device comprises;
a first layer comprising a first bottom plate portion of the capacitor device, the first bottom plate portion comprising the entirety of the first layer;
a second layer comprising a first top plate portion of the capacitor device between two second bottom plate portions;
a third layer comprising a third bottom plate portion of the capacitor device, the third bottom plate portion comprising the entirety of the third layer, wherein the third bottom plate portion is formed directly on top of the second layer; and
a set of vias connecting the first, second, and third bottom plate portions,wherein all top plate portions of capacitor devices of a same column of the array are connected to form a unified top plate; and
a set of connectors connecting the unified top plates of the columns of the array.
3 Assignments
0 Petitions
Accused Products
Abstract
A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.
18 Citations
14 Claims
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1. A capacitor device array comprising:
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an array of at least two capacitor devices arranged in columns and rows, wherein each capacitor device comprises; a first layer comprising a first bottom plate portion of the capacitor device, the first bottom plate portion comprising the entirety of the first layer; a second layer comprising a first top plate portion of the capacitor device between two second bottom plate portions; a third layer comprising a third bottom plate portion of the capacitor device, the third bottom plate portion comprising the entirety of the third layer, wherein the third bottom plate portion is formed directly on top of the second layer; and a set of vias connecting the first, second, and third bottom plate portions, wherein all top plate portions of capacitor devices of a same column of the array are connected to form a unified top plate; and a set of connectors connecting the unified top plates of the columns of the array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A capacitive digital-to-analog converter (DAC) comprising:
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a capacitor device array comprising at least three capacitor devices arranged in columns and rows, wherein each capacitor device comprises; a first layer comprising a first bottom plate portion of the capacitor device, the first bottom plate portion comprising the entirety of the first layer; a second layer comprising a first top plate portion of the capacitor device between two second bottom plate portions; a third layer comprising a third bottom plate portion of the capacitor device, the third bottom plate portion comprising the entirety of the third layer, wherein the third bottom plate portion is formed directly on top of the second layer; and a set of vias connecting the first, second, and third bottom plate portions, wherein all top plate portions of capacitor devices of a same column of the array are connected to form a unified top plate; and a set of connectors connecting the unified top plates of the columns of the array; and one or more processing circuits coupled to the capacitor device array for converting a digital code into an analog signal using the capacitor device array, wherein the at least three capacitor devices are arranged in a two dimensional array having at least one column and at least one row. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification