Semiconductor die package with internal bypass capacitors

• US 7,446,389 B2
• Filed: 07/08/2005
• Issued: 11/04/2008
• Est. Priority Date: 06/17/2004
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornelius, William P.
• Primary Examiner(s): Chu; Chris C.
• Application Number:
  US11/178,152
• Publication Number:
  US 20050280145A1
• Time in Patent Office: 1,215 Days
• Field of Search: 257/E23.079, 257/723, 257/724, 257/691, 257/678, 257/700, 257/E23.021, 257/E23.062, 257684-686, 257/532, 257/528, 361/782, 361/783
• US Class Current: 257/532
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes a package which is configured to be sandwiched between the IC device and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Claims

1. An apparatus for reducing voltage noise for an integrated circuit (IC) device, comprising:

a package which is configured to be sandwiched between the IC device and a circuit board,

wherein the package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device, wherein the package includes;

a substrate comprised of a bulk material;

top buildup layers on a top surface of the package which include traces for routing power, ground and other signals between the IC device and vias that pass through the substrate; and

bottom buildup layers on a bottom surface of the package which include traces for routing power, ground and other signals between the vias that pass through the substrate and the circuit board; and

a plurality of bypass capacitors, each including a set of internal planes, integrated into the substrate in the package between the top buildup layers and the bottom buildup layers and coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device, wherein the internal planes of the bypass capacitors extend downward from the top surface of the substrate in the package in a direction that is normal to the top surface of the substrate in the package.

2. The apparatus of claim 1, wherein the top buildup layers are comprised of an organic material.

3. The apparatus of claim 1, wherein the substrate is:

printed circuit board substrate;

or

is comprised of a copper bulk material.

4. The apparatus of claim 1, wherein the bypass capacitors axe electrically coupled to power and ground conductors on the top surface of the package, so that step currents caused by the IC device (which is coupled to the top surface of the package) enter and leave the bypass capacitors through the top surface of the package.

5. The apparatus of claim 1, wherein the IC device is a “

flip chip”

semiconductor die.