Chip package structure

• US 7,446,407 B2
• Filed: 08/31/2005
• Issued: 11/04/2008
• Est. Priority Date: 08/31/2005
• Status: Expired due to Fees

• Current Assignee: ChipMOS TECHNOLOGIES (Bermuda) LTD. (Chipmos)
• Original Assignee: ChipMOS TECHNOLOGIES (Bermuda) LTD. (Chipmos), Chipmos Technologies Incorporated (Chipmos)
• Inventors: Shen, Geng-Shin, Lin, Chun-Hung
• Primary Examiner(s): THAI, LUAN C
• Application Number:
  US11/217,978
• Publication Number:
  US 20070045835A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257/712, 257/704, 257/706, 257/707, 257/718, 257/719, 257/720, 257/E23.128, 257/E23.193, 438/121, 438/122
• US Class Current: 257/704
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Claims

1. A chip package structure, comprising:

a substrate, comprising a first surface, a second surface and a through hole;

a chip, arranged on the first surface of the substrate and electrically connected thereto, wherein the through hole of the substrate exposes a portion of the chip;

a first B-stage adhesive, arranged between the chip and the first surface of the substrate, wherein the chip is attached to the substrate through the first B-stage adhesive;

a plurality of bonding wires, connected between the chip and the second surface of the substrate via the through hole;

a heat sink, arranged on the first surface of the substrate and covering the chip;

a molding compound, arranged on the second surface of the substrate and covering the bonding wires and a portion of the substrate; and

a heat dissipation adhesive layer, arranged between the chip and the heat sink in direct contact and bonding the chip and the heat sink, wherein the heat dissipation adhesive layer is smaller than the chip size and the heat dissipation adhesive layer is a second B-stage adhesive,

wherein an area of the heat dissipation adhesive layer from the chip to the heat sink is gradually reducing.

2. The chip package structure according to claim 1, wherein the glass transition temperature of the first B-stage adhesive is between about -40°

C. and 175°

C.

3. The chip package structure according to claim 1, wherein the heat dissipation adhesive layer is a thermal paste.

4. The chip package structure according to claim 1, wherein the heat dissipation adhesive layer is a film.

5. The chip package structure according to claim 1, wherein the glass transition temperature of the second B-stage adhesive is between about -40°

C. and 175°

C.

6. The chip package structure according to claim 1, further comprising a seal resin arranged between the circumference of the chip and the first B-stage adhesive.

7. The chip package structure according to claim 1, wherein the heat sink comprises a top plate and a supporting part connected thereto, the top plate covering the chip and the supporting part being in contact with the substrate.

8. The chip package structure according to claim 7, wherein the supporting part is perpendicular to the substrate.

9. The chip package structure according to claim 7, wherein an acute angle is formed between the supporting part and the substrate.

10. The chip package structure according to claim 1, further comprising a seal resin arranged between the circumference of the supporting part and the substrate.

11. The chip package structure according to claim 1, further comprising a plurality of solder balls arranged on the second surface of the substrate.

12. A chip package structure, comprising:

a heat sink;

a chip, arranged on the heat sink; and

a film, arranged between the chip and the heat sink in direct contact, wherein the chip is attached to the heat sink through the film, and an area of the film is smaller than that of the chip, wherein the film layer is a second B-stage adhesive, wherein the area of the film varying from the chip to the heat sink is gradually reducing.

13. The chip package structure according to claim 12, wherein the heat sink comprises a top plate and a supporting part connected thereto, and the chip is arranged under the top plate.