Three dimensional integrated circuits

• US 7,446,563 B2
• Filed: 11/19/2007
• Issued: 11/04/2008
• Est. Priority Date: 07/08/2002
• Status: Expired due to Fees

• Current Assignee: Liberty Patents LLC
• Original Assignee: Tier Logic, Inc.
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US11/985,822
• Publication Number:
  US 20080074146A1
• Time in Patent Office: 351 Days
• Field of Search: 326 37- 47
• US Class Current: 326/47
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.

Claims

1. A mask configurable semiconductor device, comprising:

a programmable logic circuit having one or more high impedance nodes; and

a read only memory (ROM) element coupled to a said high impedance node to configure the programmable logic circuit, wherein the ROM element is positioned substantially above or below the programmable logic circuit.

2. The device of claim 1, wherein the ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage.

3. The device of claim 2, wherein the ROM element is customized during the fabrication process, said customization comprised of:

identifying power or ground supply voltage connection to program the programmable logic circuit to said user specification, and

customizing at least one mask in the fabrication process to provide said power or ground supply voltage connection.

4. The device of claim 3, wherein said at least one custom mask comprises a metal mask or a thru-hole mask in a multi-metal fabrication process.

5. The device of claim 1, wherein interconnect and routing signals are positioned below the ROM element and above transistors of the programmable logic circuit.

6. The device of claim 1, wherein interconnect and routing signals are positioned above the ROM element.

7. The device of claim 1, wherein interconnect and routing signals are positioned above and below the ROM element.

8. A programmable semiconductor device, comprising:

a plurality of programmable pass-gate logic elements constructed on a semiconductor substrate layer; and

a plurality of read only memory (ROM) elements positioned substantially above or below the semiconductor substrate layer, a said ROM element coupled to a said programmable pass-gate logic element to program the pass-gate logic element to a user specification.

9. The device of claim 8, wherein a said pass-gate logic element is configured by a digital input signal, the digital input signal generated by a said ROM element.

10. The device of claim 8, wherein a said pass-gate logic element comprises a high-mobility semiconductor substrate transistor.

11. The device of claim 8, wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage.

12. The device of claim 11, wherein the ROM element is customized during the fabrication process, said customization comprised of:

identifying power or ground supply voltage connection to program the programmable logic circuit to said user specification, and

customizing at least one mask in the fabrication process to provide said power or ground supply voltage connection.

13. The device of claim 12, wherein said at least one custom mask comprises a metal mask or a thru-hole mask in a multi-metal fabrication process.

14. The device of claim 10, wherein interconnect and routing signals are positioned below the ROM element and above the programmable pass-gate logic transistor.

15. The device of claim 8, wherein interconnect and routing signals are positioned above the ROM element.

16. The device of claim 8, wherein interconnect and routing signals are positioned above and below the ROM element.

17. A programmable integrated circuit (IC), wherein:

a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.

18. The IC of claim 17, further comprising a plurality of programmable metal interconnects, wherein one or more metal interconnects is configured to a user specification by a said ROM element.

19. The IC of claim 17, wherein the programmable logic circuit further comprises one or more digital inputs, a said digital input is configured to a user specification by a said ROM element.

20. The IC of claim 17, wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage as identified by said user specification.