Level shifter

• US 7,446,566 B1
• Filed: 10/16/2007
• Issued: 11/04/2008
• Est. Priority Date: 10/16/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chrudimsky, David
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/873,099
• Time in Patent Office: 385 Days
• Field of Search: 326/62, 326/63, 326/68, 326/81, 326/82, 326/83, 327/108, 327/109, 327/333
• US Class Current: 326/68
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

A level shifter circuit includes first and second cross-coupled P channel transistors, first and second cross-coupled N channel transistors, and first and second inverters. The first and second P channel transistors are coupled to receive a first power supply voltage. The first and second cross-coupled N channel transistors are coupled to the first and second P channel transistors. The first and second inverters are coupled to the first and second N channel transistors and are coupled to receive a second power supply voltage that is lower than the first power supply voltage. The first and second N channel transistors have a lower, substantially zero volts, threshold voltage and can be controlled by a low voltage signal while limiting a leakage current.

Claims

1. A level shifter circuit comprising:

a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to an output terminal, and a second current electrode;

a second transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the first transistor, and a second control electrode coupled to the control electrode of the first transistor;

a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode;

a fourth transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the second current electrode of the third transistor, and a second current electrode coupled to the control electrode of the third transistor;

a first inverter having an input terminal, and an output terminal coupled to the second current electrode of the third transistor; and

a second inverter having an input terminal coupled to the output terminal of the first inverter, and an output terminal coupled to the second current electrode of the fourth transistor.

2. The level shifter circuit of claim 1, wherein the first inverter comprises:

a fifth transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the second current electrode of the third transistor; and

a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to a third power supply voltage terminal.

3. The level shifter circuit of claim 2, wherein the second inverter comprises:

a seventh transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the second current electrode of the fourth transistor, and

an eighth transistor having a first current electrode coupled to the second current electrode of the seventh transistor, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the third power supply voltage terminal.

4. The level shifter circuit of claim 3, wherein the third and fourth transistors are N channel transistors, and wherein the third and fourth N channel transistors are characterized as having a substantially zero threshold voltage.

5. The level shifter circuit of claim 3, wherein the first, second, third, and fourth transistors have a substantially thicker gate oxide than the fifth, sixth, seventh, and eighth transistors.

6. The level shifter circuit of claim 3, wherein a first power supply voltage provided to the first power supply voltage terminal is substantially higher than a second power supply voltage provided to the second power supply voltage terminal, and wherein the third power supply voltage terminal is coupled to ground.

7. The level shifter circuit of claim 1, wherein the output terminal of the level shifter circuit is coupled to a fifth transistor, wherein the third, fourth, and fifth transistors are N channel transistors, and wherein the third and fourth transistors have a substantially lower threshold voltage than the fifth transistor.

8. The level shifter circuit of claim 1, wherein the first and second transistors are P channel transistors.

9. A level shifter circuit comprising:

a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to an output terminal, and a second current electrode;

a second transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the control electrode of the first transistor;

a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode;

a fourth transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the second current electrode of the third transistor, and a second current electrode coupled to the control electrode of the third transistor;

a fifth transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the second current electrode of the third transistor;

a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to a third power supply voltage terminal;

a seventh transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the second current electrode of the fourth transistor, and

an eighth transistor having a first current electrode coupled to the second current electrode of the seventh transistor, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the third power supply voltage terminal;

wherein the first power supply voltage terminal is for receiving a first power supply voltage, the second power supply voltage terminal is for receiving a second power supply voltage, and the third power supply voltage is coupled to ground, and wherein the second power supply voltage is between ground and the first power supply voltage.

10. The level shifter circuit of claim 9, wherein a threshold voltage of each of the third and fourth transistors is lower than the second power supply voltage.

11. The level shifter circuit of claim 9, wherein a threshold voltage of each of the third and fourth transistors is substantially zero volts.

12. The level shifter circuit of claim 9, wherein the first, second, fifth, and seventh transistors are P channel transistors, and the third, fourth, sixth, and eighth transistors are N channel transistors.

13. The level shifter circuit of claim 9, wherein the first, second, third, and fourth transistors have a substantially thicker gate oxide than the fifth, sixth, seventh, and eighth transistors.

14. The level shifter circuit of claim 9, wherein a threshold voltage of each of the third and fourth transistors is in a range from −

0.2 volts to +0.3 volts.

15. The level shifter circuit of claim 9, wherein the second current electrode of the second transistor is coupled to a control electrode of a ninth transistor, wherein the third, fourth, and ninth transistors are N channel transistors, and wherein each of the third and fourth transistors have a substantially lower threshold voltage than the ninth transistor.

16. A level shifter circuit comprising:

a first P channel transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to an output terminal, and a second current electrode;

a second P channel transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to the control electrode of the first P channel transistor;

a first N channel transistor having a first current electrode coupled to the second current electrode of the first P channel transistor, a control electrode, and a second current electrode;

a second N channel transistor having a first current electrode coupled to the second current electrode of the second P channel transistor, a control electrode coupled to the second current electrode of the first N channel transistor, and a second current electrode coupled to the control electrode of the first N channel transistor;

a first inverter having an input terminal, a power supply voltage terminal, and an output terminal coupled to the second current electrode of the first N channel transistor; and

a second inverter having an input terminal coupled to the output terminal of the first inverter, a power supply voltage terminal, and an output terminal coupled to the second current electrode of the second N channel transistor;

wherein a first power supply voltage is provided to the first power supply voltage terminal, and a second power supply voltage is provided to the power supply voltage terminals of the first and second inverters, wherein the second power supply voltage is between the first power supply voltage and ground potential.

17. The level shifter circuit of claim 16, wherein a threshold voltage of each of the first and second N channel transistors is lower than the second power supply voltage.

18. The level shifter circuit of claim 16, wherein a threshold voltage of each of the first and second N channel transistors is substantially zero volts.

19. The level shifter circuit of claim 16, wherein a threshold voltage of each of the first and second N channel transistors is in a range of −

0.2 volts to +0.3 volts.

20. The level shifter circuit of claim 16, wherein each of the first and second inverters comprises a P channel transistor coupled in series with an N channel transistor, wherein the P channel transistor and the N channel transistor coupled between the power supply voltage terminals of the first and second inverters and ground, and wherein each of the first and second P channel transistors and the first and second N channel transistors have a thicker gate dielectric than the P channel transistor and the N channel transistor of the first and second inverters.