System for synchronization of multi-sensor data

• US 7,446,694 B1
• Filed: 05/30/2007
• Issued: 11/04/2008
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: ARRIS Enterprises LLC (CommScope Holding Company, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Nasir, Irfan, Mohamed, Magdi A., Ishtiaq, Faisal, Ahmed, Mohamed I.
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US11/755,341
• Time in Patent Office: 524 Days
• Field of Search: 341140-170
• US Class Current: 341/160
• CPC Class Codes: H03M 1/1255 Synchronisation of the sampling frequency or phase to the input frequency or phase

Abstract

A multi-sensor system includes a first analog sensor sub-system, a second analog sensor sub-system, and a system for synchronizing the outputs of the first and second analog sub-systems. Each analog sensor sub-system includes a sensor that produces an analog output. Each sensor is coupled to analog circuitry that processes the output from the sensor. The system for synchronizing the outputs of the first and second analog sensor sub-systems simultaneously inserts a marker into the outputs of the first and second analog sensors. Then, the outputs of the analog circuitry of the first and second analog sub-systems are synchronized based upon the marker. The marker signal may be produced using a Barker sequence signal generator.

Claims

1. A multi-sensor system, which comprises:

a first analog sub-system, said first analog sub-system including a first analog sensor, said first analog sensor producing an output, and first analog circuitry coupled to said first analog sensor, said first analog circuitry processing said output from said first analog sensor;

a second analog sub-system, said second analog sub-system including a second analog sensor, said second analog sensor producing an output, and second analog circuitry coupled to said second analog sensor, said first analog circuitry processing said output from said second analog sensor; and

,

means for synchronizing the outputs of said first and second analog circuitry, wherein said means for synchronizing the outputs of said first and second analog circuitry comprises;

a first analog multiplexer coupled between said first analog sensor and said first analog circuitry;

a second analog multiplexer coupled between said second analog sensor and said second analog circuitry; and

,

a marker signal generator coupled to said first and second analog multiplexers.

2. The system as claimed in claim 1, wherein said marker signal generator comprises:

a digital signal generator; and

,

a digital-to-analog converter coupled between said digital signal generator and said analog multiplexers.

3. The system as claimed in claim 2, wherein said digital signal generator comprises:

a Barker sequence generator.

4. The system as claimed in claim 1, including:

a first analog-to-digital converter coupled to the output of said first analog circuitry; and

,

a second analog-to-digital converter coupled to the output of said second analog circuitry.

5. The system as claimed in claim 4, wherein said means for synchronizing the outputs of said first and second analog circuitry comprises:

a first buffer coupled to said first analog-to-digital converter;

a second buffer coupled to said second analog-to-digital converter;

a first correlation device coupled to said first buffer; and

,

a second correlation device coupled to said second buffer.

6. The system as claimed in claim 5, wherein said means for synchronizing the outputs of said first and second analog circuitry based upon said marker further comprises:

a first peak detector coupled to said first correlation device;

a second peak detector coupled to said second correlation device; and

,

an address generation unit coupled to said first and second peak detectors and to said first and second buffers.

7. The system as claimed in claim 4, wherein:

said first analog-to-digital converter is coupled to the output of said first analog circuitry through a first wireless link; and

,

said second analog-to-digital converter is coupled to the output of said second analog circuitry through a second wireless link.

8. The system as claimed in claim 1, wherein said means for synchronizing the outputs of said first and second analog circuitry comprises:

a beacon coupled to said first and second sensor sub-systems through wireless links.

9. The system as claimed in claim 4, wherein said means for synchronizing the outputs of said first and second analog circuitry further comprises:

means for detecting said marker signal in the output of said first analog-to-digital converter; and

means for detecting said marker signal in the output of said second analog-to-digital converter.

10. The system as claimed in claim 9, wherein said means for detecting said marker signals in the outputs of said first and second analog-to-digital converter comprises:

a first correlation device coupled to the output of said first analog-to-digital converter;

a first peak detector coupled to said first correlation device;

a second correlation device coupled to the output of said second analog-to-digital converter; and

,

a second peak detector coupled to said second correlation device.

11. The system as claimed in claim 10, wherein said first and second correlation devices each comprise a cross-correlator.

12. The system as claimed in claim 9, wherein said means for synchronizing the outputs of said first and second analog circuitry further comprises:

means for synchronizing said marker signal detected in the output of said first analog-to-digital converter with said marker signal detected in the output of said second analog-to-digital converter.

13. The system as claimed in claim 10, wherein said means for synchronizing the outputs of said first and second analog circuitry further comprises:

a first buffer coupled to the output of said first analog-to-digital converter;

a second buffer coupled to the output of said second analog-to-digital converter; and

,

said means for synchronizing said marker signal detected in the output of said first analog-to-digital converter with said marker signal detected in the output of said second analog-to-digital converter includes means for shifting data in one of said buffers.

14. The system as claimed in claim 13, wherein said means for shifting data in one of said buffers comprises an address generation unit coupled to said one of said buffers.

15. The system as claimed in claim 13, wherein said means for synchronizing the outputs of said first and second analog circuitry further comprises:

a first correlation device coupled to said first buffer;

a second correlation device coupled to said second buffer; and

,

a first peak detector coupled to said first correlation device;

a second peak detector coupled to said second correlation device; and

,

said means for synchronizing said marker signal detected in the output of said first analog-to-digital converter with said marker signal detected in the output of said second analog-to-digital converter includes means for shifting data in one of said buffers comprises means for detecting a time difference between detecting said marker signal in the output of said first analog-to-digital converter and detecting said marker signal in the output of said second analog-to-digital converter.

16. A sensor sub-system, which comprises:

an analog sensor, said analog sensor producing an output;

analog circuitry coupled to said analog sensor, said analog circuitry processing said output from said analog sensor; and

,

means for inserting a synchronizing marker into the output of said analog sensor said means for inserting said synchronizing marker into the output of said analog sensor including;

an analog multiplexer coupled between said analog sensor and said analog circuitry;

a digital-to-analog converter coupled to said analog multiplexer; and

,

a digital signal generator coupled to said digital-to-analog converter.

17. The sub-system as claimed in claim 16, wherein said digital signal generator comprises:

a Barker sequence generator.

18. The sub-system as claimed in claim 16, wherein said means for inserting said synchronizing marker into the output of said analog sensor comprises:

a wireless module coupled to said digital-to-analog converter.

19. The sub-system as claimed in claim 16, including:

a wireless module coupled to said analog circuitry.

20. The sub-system as claimed in claim 19, including:

an analog-to-digital converter coupled between said analog circuitry and said wireless module.

21. A multi-sensor synchronization system, which comprises:

means for receiving an output signal from a first sensor sub-system, said means for receiving said output signal from said first sensor sub-system including a first input buffer;

means for receiving an output signal from a second sensor sub-system, said means for receiving said output signal from said second sensor including a second input buffer;

a first correlation device coupled to said first input buffer;

a second correlation device coupled to said second input buffer;

a first peak detector coupled to said first correlation device;

a second peak detector coupled to said second correlation device;

an address generation unit coupled to said first and second peak detectors and to said first and second buffers; and

,

means for sending a synchronization marker signal to said first and second sensor sub-systems.

22. The system as claimed in claim 21, wherein said means for sending said synchronization marker signal to said first and second sensors comprises:

a synchronization signal generator.

23. The system as claimed in claim 22, wherein said synchronization signal generator comprises:

a Barker sequence generator.

24. The system as claimed in claim 22, wherein said means for sending said synchronization signal to said first and second sensors further comprises:

a wireless module coupled to said synchronization signal generator.

25. The system as claimed in claim 21, wherein said means for receiving said output signal from a first sensor comprises:

a wireless module coupled to said first input buffer.