Video and graphics system with an integrated system bridge controller

• US 7,446,774 B1
• Filed: 08/18/2000
• Issued: 11/04/2008
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A.
• Primary Examiner(s): Brier; Jeffery A.
• Application Number:
  US09/642,458
• Time in Patent Office: 3,000 Days
• Field of Search: 345/115, 345/502, 345/520, 345/536, 345/508, 345/519, 348/425.3, 348/554, 348/571, 713/323, 713/340, 725/116, 725/217, 725/131, 725/117, 710/100
• US Class Current: 345/519
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 2340/06 Colour space transformation
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/112 : according to a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/16 : for a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/186 : the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/20 : using video object coding
• CPC Class Codes: H04N 19/27 : involving both synthetic and natural picture components, e.g. synthetic natural hybrid coding [SNHC]
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/80 : Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation H04N19/635, H04N19/86 take precedence
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers
• CPC Class Codes: H04N 9/75 : Chroma key
• CPC Class Codes: H04N 9/78 : for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter

Abstract

A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.

Claims

1. A system on a single integrated circuit chip comprising:

an MPEG Transport processor for receiving a plurality of MPEG Transport streams, at least one of the MPEG Transport streams including MPEG video data;

an MPEG video decoder for decoding the MPEG video data using an external memory to generate video for displaying;

a display engine for processing graphics to be blended with the video using the external memory; and

a system bridge controller having a north bridge function disposed between a CPU and a plurality of peripheral devices for coupling the CPU to the plurality of peripheral devices,

wherein the MPEG video decoder, the display engine and the system bridge controller are implemented on the single integrated circuit chip,

wherein the plurality of peripheral devices are situated externally to the single integrated circuit chip, and

wherein the external memory has a unified memory architecture, such that the external memory is concurrently used by the CPU through the system bridge controller as at least a part of its main memory, the display engine for processing the graphics, and the MPEG decoder for decoding the MPEG video data.

2. A system on a single integrated circuit chip comprising:

an MPEG Transport processor for receiving a plurality of MPEG Transport streams, at least one of the MPEG Transport streams including MPEG video data;

an MPEG video decoder for processing the MPEG video data to generate video for displaying; and

a system bridge controller having a north bridge function disposed between a CPU and a plurality of peripheral devices for coupling the CPU to at least one of the MPEG Transport processor and the MPEG video decoder, and to the plurality of peripheral devices, wherein the MPEG Transport processor, the MPEG video decoder and the system bridge controller are implemented on the single integrated circuit chip, and

wherein the plurality of peripheral devices are situated externally to the single integrated circuit chip.

3. The system of claim 2 wherein the system bridge controller is capable of performing format conversion between big-endian data and little-endian data, between the CPU and one or more of the plurality of peripheral devices.

4. The system of claim 3 further comprising other components for processing video and graphics on the single integrated circuit chip, and wherein the system bridge controller is capable of performing format conversion between big-endian data and little-endian data, between the CPU and at least one of the MPEG video decoder and the other components for processing video and graphics.

5. The system of claim 2 wherein the plurality of peripheral devices include one or more PCI devices, and wherein the system bridge controller includes a PCI bridge for coupling the CPU to the one or more PCI devices.

6. The system of claim 5 wherein the PCI bridge is capable of performing a DMA function between the one or more PCI devices and an external memory.

7. The system of claim 5 wherein the PCI bridge is capable of performing format conversion between big-endian data used in the CPU and little-endian data used in the one or more PCI devices.

8. The system of claim 5 wherein the PCI bridge is capable of performing format conversion between little-endian data used in the CPU and big-endian data used in the one or more PCI devices.

9. The system of claim 2 wherein the plurality of peripheral devices include one or more I/O devices, and wherein the system bridge controller includes an I/O bus bridge for coupling the CPU to the one or more I/O devices.

10. The system of claim 9 wherein the I/O bus bridge is capable of performing a DMA function between the CPU and the one or more I/O devices.

11. The system of claim 9 wherein the one or more I/O devices include a device selected from a group consisting of ROM, RAM, flash memory and 68000-compatible peripheral devices.

12. The system of claim 9 wherein the I/O bus bridge is capable of performing format conversion between big-endian data used in the CPU and little-endian data used in the one or more I/O devices.

13. The system of claim 9 wherein the I/O bus bridge is capable of performing format conversion between little-endian data used in the CPU and big-endian data used in the one or more I/O devices.

14. The system of claim 2 wherein the system bridge controller includes a CPU interface block for coupling the CPU to the MPEG video decoder.

15. The system of claim 14 wherein the CPU interface block is coupled with the CPU selected from a group consisting of a MIPS processor, an SH3 processor and an SH4 processor.

16. The system of claim 14 wherein the CPU interface block is capable of performing burst accesses of the CPU in both read and write directions.

17. The system of claim 14 wherein the CPU interface block includes one or more buffers used to resolve a speed difference between the CPU and external SDRAM devices.

18. The system of claim 14 wherein the CPU interface block is capable of performing format conversion between big-endian data used in the CPU and little-endian data used in the MPEG video decoder.

19. The system of claim 14 wherein the CPU interface block is capable of performing format conversion between little-endian data used in the CPU and big-endian data used in the MPEG video decoder.

20. The system of claim 2 wherein the video includes at least one HDTV video.

21. The system of claim 2 wherein the video includes at least one SDTV video.

22. The system of claim 2, wherein the system bridge controller is capable of performing format conversion between big-endian data and little-endian data, between the CPU and at least one of the MPEG Transport processor and the MPEG video decoder, and one or more of the plurality of peripheral devices.

23. The system of claim 9, wherein the CPU has a first data width that is a multiple of a second data width of at least one of the one or more I/O devices, and wherein the I/O bus bridge automatically converts a data access with the first data width by the CPU into multiple data accesses with the second data width to support said at least one of the one or more I/O devices having the second data width.

24. The system of claim 2, further comprising a video compositor implemented on the single integrated circuit chip, wherein the video compositor blends the video generated by the MPEG video decoder with graphics.

25. The system of claim 24, further comprising a graphics blender implemented on the single integrated circuit chip, wherein the graphics blender blends two or more graphics windows to generate the graphics provided to the video compositor.

26. A method of coupling a CPU to other devices and to process MPEG video data, the method comprising:

coupling the CPU to a plurality of peripheral devices via a system bridge controller having a north bridge function implemented on an integrated circuit chip,

receiving a plurality of MPEG Transport streams using an MPEG Transport processor implemented on the integrated circuit chip, at least one of the MPEG Transport streams including the MPEG video data; and

decoding the MPEG video data using an MPEG video decoder implemented on the integrated circuit chip to generate video for displaying,

wherein the plurality of peripheral devices are situated externally to the integrated circuit chip.

27. The method of claim 26 wherein coupling the CPU to a plurality of peripheral devices comprises performing format conversion between big-endian data and little-endian data, between the CPU and one or more of the plurality of peripheral devices.

28. The method of claim 26 wherein the integrated circuit chip contains one or more internal components, and the method further comprises coupling the CPU to at least one of the one or more internal components via the system bridge controller.

29. The method of claim 28 wherein coupling the CPU to at least one of the one or more internal components comprises performing format conversion between big-endian data and little-endian data, between the CPU and at least one of the one or more internal components.

30. The method of claim 26 wherein coupling the CPU to a plurality of peripheral devices comprises the step of coupling the CPU to one or more PCI devices.

31. The method of claim 30 further comprising performing a DMA function between the one or more PCI devices and an external memory.

32. The method of claim 30 wherein coupling the CPU to one or more PCI devices comprises performing format conversion between big-endian data used in the CPU and little-endian data used in the one or more PCI devices.

33. The method of claim 30 wherein coupling the CPU to one or more PCI devices comprises performing format conversion between little-endian data used in the CPU and big-endian data used in the one or more PCI devices.

34. The method of claim 26 wherein coupling the CPU to a plurality of peripheral devices comprises coupling the CPU to one or more I/O devices, the I/O devices being coupled to the integrated circuit chip via a bus different from a PCI bus.

35. The method of claim 34 wherein coupling the CPU to one or more I/O devices comprises performing a DMA function between the CPU and the one or more I/O devices.

36. The method of claim 34 wherein the one or more I/O devices include one or more devices selected from a group consisting of ROM, RAM, flash memory and 68000-compatible peripheral devices.

37. The method of claim 34 wherein coupling the CPU to one or more I/O devices comprises performing format conversion between big-endian data used in the CPU and little-endian data used in the one or more I/O devices.

38. The method of claim 28 wherein coupling the CPU to one or more I/O devices comprises performing format conversion between little-endian data used in the CPU and big-endian data used in the one or more I/O devices.

39. The method of claim 28 wherein coupling the CPU to at least one of the one or more internal components comprises performing burst accesses of the CPU in both read and write directions.

40. The method of claim 28 wherein coupling the CPU to at least one of the one or more internal components comprises resolving a speed difference between the CPU and external SDRAM devices.

41. The method of claim 28 wherein coupling the CPU to at least one of the one or more internal components comprises performing format conversion between big-endian data used in the CPU and little-endian data used in the MPEG video decoder.

42. The method of claim 28 wherein coupling the CPU to at least one of the one or more internal components comprises performing format conversion between little-endian data used in the CPU and big-endian data used in the MPEG video decoder.

43. The method of claim 26 wherein the video generated by decoding the MPEG video data includes at least one HDTV video.

44. The method of claim 34, wherein the CPU has a first data width that is a multiple of a second data width of at least one of the one or more I/O devices, and wherein coupling the CPU to one or more I/O devices comprises automatically converting a data access with the first data width by the CPU into multiple data accesses with the second data width to support said at least one of the one or more I/O devices having the second data width.