Memory with retargetable memory cell redundancy

• US 7,447,066 B2
• Filed: 11/08/2005
• Issued: 11/04/2008
• Est. Priority Date: 11/08/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Cedar, Yoram
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/270,410
• Publication Number:
  US 20070103978A1
• Time in Patent Office: 1,092 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.17, 365/185.33, 365/200, 365/225.7, 365/185.11
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

Claims

1. A nonvolatile memory array, comprising:

a first column of memory cells that contains a defective cell and nondefective cells;

a second column of memory cells that is a redundant column that contains only data relocated from outside the second column of memory cells; and

the defective cell individually mapped to a redundant cell in the second column such that data to be stored in the defective cell is stored in the redundant cell, the defective cell and the redundant cell in the same row, the second column containing no data mapped from the nondefective cells of the first column.

2. The memory array of claim 1 further comprising a third column that is considered defective and does not store data, all data for the third column stored in a fourth column that is a redundant column.

3. The memory array of claim 2 wherein the third column is considered defective because it has a number of defective cells that exceeds a threshold number that is greater than one, and that is less than the number of cells in the third column.

4. The memory array of claim 1 wherein the defective cell and the redundant cell are in the same block and are not separately erasable.

5. The memory array of claim 4 wherein the mapping of the defective cell to the redundant cell is recorded in another block of the memory array.

6. The memory array of claim 1 wherein the second column contains additional data that is mapped from defective cells in columns other than the first column.

7. The memory array of claim 1 wherein the mapping of the defective cell to the redundant cell is recorded outside the nonvolatile memory array.

8. The memory array of claim 1 wherein the mapping of the defective cell to the redundant cell is permanently recorded using a fuse or antifuse.

9. The memory array of claim 1 wherein the memory array has a NAND structure.

10. The memory array of claim 1 wherein an individual cell of the first or second column contains two or more bits of data.

11. The memory array of claim 1 wherein, subsequently, when access to the defective cell is attempted, the redundant cell is accessed instead.

12. The memory array of claim 11 wherein, when access to the defective cell is attempted, both the row and column of the defective cell are compared to a defect map to determine that the defective cell is defective.

13. The memory array of claim 12 wherein the row and column are compared to the defect map by a dedicated state machine connected to the memory array.

14. The memory array of claim 12 wherein the row and column are compared to the defect map by a controller that also performs other memory management functions.

15. A nonvolatile NAND flash memory array, comprising:

a first column of NAND strings that contains a defective string and nondefective strings;

a second column of NAND strings that is a redundant column that contains only data relocated from outside the second column of NAND strings;

the defective NAND string individually mapped to a redundant NAND string in the second column such that data to be stored in the defective NAND string is stored in the redundant NAND string, the second column containing no data mapped from the nondefective NAND strings of the first column;

a third column that is considered defective because it has a number of defective strings that exceeds a threshold number; and

The entire third column mapped to a redundant fourth column to replace the third column.

16. The nonvolatile NAND flash memory array of claim 15 wherein the defective string and the redundant NAND string are in a common block.