Method for programming a multilevel memory

• US 7,447,068 B2
• Filed: 03/19/2007
• Issued: 11/04/2008
• Est. Priority Date: 03/19/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lin, Yung-Feng, Tsai, Fu-Kai
• Primary Examiner(s): Auduong; Gene N.
• Application Number:
  US11/723,352
• Publication Number:
  US 20080232164A1
• Time in Patent Office: 596 Days
• Field of Search: 365/185.03, 365/185.21, 365/185.22, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator

Abstract

A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than the first PV level of the targeted programmed state such that at least one bit of them has a Vt level larger than a second PV level corresponding to a targeted programmed state, wherein the second PV level of the targeted programmed state is larger than the corresponding first PV level; and programming only the bits of the memory with a Vt level lower than the first PV level of the targeted programmed state such that each of them has a Vt level larger than the first PV level of the targeted programmed state.

Claims

1. A method for programming a multi-level cell (MLC) memory, the MLC memory comprising a plurality of bits, each bit having a plurality of programmed states, each programmed state having a first program verify (PV) level, the method comprising:

(a) programming the bits of the memory having a threshold voltage (Vt) level lower than the first PV level of a targeted programmed state such that at least one bit of them has a Vt level higher than a second PV level corresponding to the targeted programmed state, wherein the second PV level of the targeted programmed state is higher than the corresponding first PV level; and

(b) programming only the bits of the memory with a Vt level lower than the first PV level of the targeted programmed state such that each of them has a Vt level higher than the first PV level of the targeted programmed state.

2. The method according to claim 1, wherein the multi-level cell memory is a charge trapping memory with oxide-nitride-oxide (ONO) structure.

3. The method according to claim 1, wherein the multi-level cell memory is a flash memory.

4. The method according to claim 1, wherein each bit has four programmed states 11, 01, 00 and 10.

5. The method according to claim 4, wherein the difference between the first PV level and the second PV level is about 300 mV˜

400 mV.

6. The method according to claim 5, wherein a read margin between the adjacent programmed states is about 400 mV˜

500 mV.

7. The method according to claim 6, wherein the first PV level and the second PV level of the programmed state 01 are respectively 5.1V and 5.5V, the first PV level and the second PV level of the programmed state 00 are respectively 4.3V and 4.7V, the first PV level and the second PV level of the programmed state 10 are respectively 3.5V and 3.9V, and the first PV level and the second PV level of the programmed state 11 are respectively 2.0V and 3.1V.

8. The method according to claim 4, wherein a word line bias of each programmed bit in step (a) is larger than that in step (b).

9. The method according to claim 8, wherein a word line bias of each programmed bit has a voltage 9.5V for the targeted programmed state 01, a voltage 8.5V for the targeted programmed state 00 and a voltage 7.5V for the targeted programmed state 10 in the step (a).

10. The method according to claim 4, wherein a bit line bias of each programmed bit is increased from 4.0V to 4.5V for the targeted programmed state 01, increased from 3.5V to 4.0V for the targeted programmed state 00 and increased from 3.0V to 3.5V for the targeted programmed state 10 in the step (a).

11. The method according to claim 8, wherein the word line bias of each programmed bit has a constant voltage equal to the first PV level and a bit line bias of each programmed bit has a constant voltage smaller than a maximum of the voltage range in the step (a) corresponding to the targeted programmed state in the step (b).

12. The method according to claim 11, wherein the bit line bias of each programmed bit has the constant voltage 4V˜

4.5V for the targeted programmed state 01, 3.5V˜

4.0V for the targeted programmed state 00 and 3.0V˜

3.5V for the targeted programmed state 10 in the step (b).

13. The method according to claim 1, wherein a program shot number of the step (a) is 1˜

3.

14. The method according to claim 1, wherein the step (a) comprises determining if every bit of the memory has a Vt level higher than the first PV level of the targeted programmed state and if yes, stopping the method.

15. The method according to claim 1, wherein the step (b) comprises recording the bits of the memory with a Vt level higher than the first PV level of the targeted programmed state.