Method and system for synchronizing communications links in a hub-based memory system

• US 7,447,240 B2
• Filed: 03/29/2004
• Issued: 11/04/2008
• Est. Priority Date: 03/29/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: James, Ralph
• Primary Examiner(s): Ngo; Ricky
• Assistant Examiner(s): Yuen; Kan
• Application Number:
  US10/813,040
• Publication Number:
  US 20050213611A1
• Time in Patent Office: 1,681 Days
• Field of Search: 370/248, 370/249, 370/503, 370/512, 370/520, 711/154, 711/167
• US Class Current: 370/516
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller. The method includes synchronizing each upstream and downstream link. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, the next adjacent clockwise link is signaled that the prior clockwise link has been synchronized. The method detects through the upstream link coupled between the controller and the first memory module when all links have been synchronized. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, each link is enabled. The method detects through the upstream link coupled between the controller and first memory module when all links have been enabled.

Claims

1. A memory hub, comprising:

a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation;

a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation;

an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation; and

an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation.

2. The memory hub of claim 1 wherein the enablement command comprises a No Operation command.

3. The memory hub of claim 1 wherein the downstream and upstream transmission interfaces adjust the value of the corresponding test data signals responsive to the inversion signal by inverting the test data signals.

4. The memory hub of claim 1 further comprising local hub circuitry coupled to the interfaces, the local control circuitry operable process memory requests during the normal mode of operation and to develop corresponding memory signals on a memory bus output.

5. The memory hub of claim 4, wherein the memory signals comprise address, data, and control signals.

6. The memory hub of claim 1 wherein the reception interfaces include optical interfaces to receive data words from an optical communications link.

7. The memory hub of claim 6 wherein the downstream reception interface and the upstream transmission interface are configured to be coupled to the same optical communications link, and wherein the downstream transmission interface and the upstream reception interface are configured to be coupled to the same optical communications link.

8. The memory hub of claim 7 wherein the optical communications link comprises an optical fiber.

9. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation;

a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation;

an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation;

an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation; and

local hub circuitry coupled to the interfaces and to the memory devices.

10. The memory module of claim 9 wherein the enablement command comprises a No Operation command.

11. The memory module of claim 9 wherein the downstream and upstream transmission interfaces adjust the value of the corresponding test data signals responsive to the inversion signal by inverting the test data signals.

12. The memory module of claim 9 wherein the memory signals comprise address, data, and control signals.

13. The memory module of claim 9 wherein the memory devices comprise SDRAMs.

14. The memory module of claim 9 wherein the reception interfaces include optical interfaces to receive data words from an optical communications link.

15. The memory module of claim 14 wherein the downstream reception interface and the upstream transmission interface are configured to be coupled to the same optical communications link, and wherein the downstream transmission interface and the upstream reception interface are configured to be coupled to the same optical communications link.

16. The memory module of claim 15 wherein the optical communications link comprises an optical fiber.

17. A memory system, comprising:

a plurality of memory modules coupled in series, each module being coupled to adjacent modules through respective downstream and upstream high-speed communications links, each memory module comprising;

a plurality of memory devices; and

a memory hub, comprising;

a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation;

a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation;

an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation;

an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation; and

local hub circuitry coupled to the interfaces and to the memory devices; and

a system controller coupled to a first one of the memory modules through respective downstream and upstream high-speed communications links.

18. The memory system of claim 17 wherein the system controller further comprises:

a downstream transmission interface coupled to the downstream high-speed communications link, the interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to an inversion signal, and operable in the enablement mode responsive to an enablement signal to provide an enablement command on the output and to place the downstream transmission interface into the normal mode of operation; and

an upstream reception interface coupled to the upstream high-speed communications link, the interface operable in the initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate the inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation, and further operable responsive to receiving the enablement command to generate a ready signal indicating all the memory modules have been synchronized.

19. The memory system of claim 17 wherein the enablement command comprises a No Operation command.

20. The memory system of claim 17 wherein the downstream and upstream transmission interfaces adjust the value of the corresponding test data signals responsive to the inversion signal by inverting the test data signals.

21. The memory system of claim 17 wherein the memory signals comprise address, data, and control signals.

22. The memory system of claim 17 wherein the memory devices comprise SDRAMs.

23. The memory system of claim 17 wherein the reception interfaces include optical interfaces to receive data words from an optical communications link.

24. The memory system of claim 23 wherein in each memory module the downstream reception interface and the upstream transmission interface are coupled to the same optical communications link, and wherein the downstream transmission interface and the upstream reception interface are coupled to the same optical communications link.

25. The memory system of claim 24 wherein the optical communications link comprises an optical fiber.

26. A computer system, comprising:

a processor;

a system controller coupled to the processor through respective downstream and upstream high-speed communications links;

a memory system, comprising;

a plurality of memory modules coupled in series, each module being coupled to adjacent modules through respective downstream and upstream high-speed communications links, and a first one of the modules being coupled to the processor through respective downstream and upstream high-speed communications links, each memory module comprising;

a plurality of memory devices; and

a memory hub, comprising;

a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation;

a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation;

an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation;

an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation; and

local hub circuitry coupled to the interfaces and to the memory devices.

27. The computer system of claim 26 wherein the system controller further comprises:

a downstream transmission interface coupled to the downstream high-speed communications link, the downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to an inversion signal, and operable in the enablement mode responsive to an enablement signal to provide an enablement command on the output and to place the downstream transmission interface into the normal mode of operation; and

an upstream reception interface coupled to the upstream high-speed communications link, the upstream reception interface operable in the initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate the inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation, and further operable responsive to receiving the enablement command to generate a ready signal indicating all the memory modules have been synchronized.

28. The memory system of claim 26 wherein the enablement command comprises a No Operation command.

29. The computer system of claim 26 wherein the memory devices comprise SDRAMs.

30. The computer system of claim 26 wherein each of the high-speed links comprises an optical communications link.

31. The computer system of claim 26 wherein the processor comprises a central processing unit (CPU).