Non-volatile memory sharing apparatus for multiple processors and method thereof

• US 7,447,846 B2
• Filed: 04/12/2006
• Issued: 11/04/2008
• Est. Priority Date: 04/12/2006
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Yeh, Hsin-Chung
• Primary Examiner(s): Bragdon; Reginald G.
• Assistant Examiner(s): Dihn; Ngoc V
• Application Number:
  US11/279,562
• Publication Number:
  US 20070245092A1
• Time in Patent Office: 937 Days
• Field of Search: None
• US Class Current: 711/147
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

A multiple processor system includes a plurality of processors including a first processor and a second processor; a program code storage module coupled to the first processor, the program code storage module for storing program code including first program code for the first processor and second program code for the second processor; and a processor bridge coupled between the first processor and the second processor; wherein the first processor executes the first program code, the second processor is for sending an access request requesting data corresponding to the second program code to the processor bridge; the first processor is for retrieving the access request from the processor bridge, fetching the data from the second program code in the program code storage module according to the access request, and delivering the data to the processor bridge; and the second processor is further for fetching the data from the processor bridge.

Claims

1. A non-volatile memory sharing system comprising:

a plurality of processors comprising at least a first processor and a second processor;

a non-volatile memory coupled to the first processor, the non-volatile memory for storing a plurality of program codes or data comprising at least a first program code for the first processor and a second program code or data for the second processor; and

a processor bridge coupled between the first processor and the second processor;

wherein the first processor is for executing the first program code directly from the non-volatile memory, the second processor is for sending an access request requesting data corresponding to the second program code to the processor bridge;

the first processor is for retrieving the access request from the processor bridge, fetching the data from the second program code in the non-volatile memory according to the access request, and delivering the data to the processor bridge; and

the second processor is further for fetching the data from the processor bridge.

2. The non-volatile memory sharing system of claim 1, wherein the first processor is further for approving the access request and fetching the data from the second program code in the non-volatile memory according to the access request if the access request is approved;

the access request only being approved by the first processor if the access request requests data from the second program code.

3. The non-volatile memory sharing system of claim 1, wherein the plurality of processors further comprise a third processor being coupled to the processor bridge, the third processor for sending a second access request requesting second data corresponding to third program code to the processor bridge;

the first processor is for retrieving the second access request from the processor bridge, fetching the second data from the third program code in the non-volatile memory according to the second access request, and delivering the second data to the processor bridge; and

the third processor is further for fetching the second data from the processor bridge;

wherein the non-volatile memory is further for storing the third program code or second data for the third processor.

4. The non-volatile memory sharing system of claim 3, wherein the second processor is for executing the second program code after the data corresponding to the second program code is fetched from the processor bridge, and the third processor is for executing the third program code after the second data corresponding to the third program code is fetched from the processor bridge.

5. The non-volatile memory sharing system of claim 4 further comprising a first random access memory (RAM) module coupled to the second processor and a second RAM module coupled to the third processor;

the second processor further for storing the second program code into the first RAM module after the data corresponding to the second program code is fetched from the processor bridge, and for executing the second program code from the first RAM module;

the third processor further for storing the third program code into the second RAM module after the second data corresponding to the third program code is fetched from the processor bridge, and for executing the third program code from the second RAM module.

6. The non-volatile memory sharing system of claim 5 wherein the second processor is for performing a first program code transfer operation comprising sending a plurality of access requests to the processor bridge to thereby completely obtain the second program code from the program code storage module, and to completely store the second program code into the first RAM module prior to executing the second program code from the first RAM module;

and the third processor is for performing a second program code transfer operation comprising sending a plurality of second access requests to the processor bridge to thereby completely obtain the third program code from the program code storage module, and to completely store the third program code into the second RAM module prior to executing the third program code from the second RAM module.

7. The non-volatile memory sharing system of claim 6 wherein the second processor is for performing the first program code transfer operation immediately upon system startup, and executing the second program code after completion of the first program code transfer operation;

the third processor for performing the second program code transfer operation immediately upon system startup, and executing the third program code after completion of the second program code transfer operation.

8. The non-volatile memory sharing system of claim 3 wherein the second processor is further for sending a first write request to the processor bridge, and the third processor is further for sending a second write request to the processor bridge;

the first write request comprising first write data and a first write address for the first write data to be stored in the non-volatile memory, and the second write request comprising second write data and a second write address for the second write data to be stored in the non-volatile memory; and

the first processor further for retrieving the write request from the processor bridge, storing the first write data in the non-volatile memory at the first write address according to the first write request, retrieving the second write request from the processor bridge, and storing the second write data in the non-volatile memory at the second write address according to the second write request.

9. The non-volatile memory sharing system of claim 3, wherein the first processor is further for approving the access request and fetching the data from the second program code in the non-volatile memory according to the access request if the access request is approved, and the first processor is further for approving the second access request and fetching the second data from the third program code in the non-volatile memory according to the second access request if the second access request is approved;

the access request only being approved if the access request requests data from the second program code; and

the second access request only being approved if the second access request requests second data from the third program code.

10. The non-volatile memory sharing system of claim 1 wherein the non-volatile memory is divided into sections according to a number of processors in the multiple processor systems, and program code corresponding to a particular processor is stored in a section of the non-volatile memory corresponding to the particular processor.

11. A memory sharing method for a multiple processor system comprising a plurality of processors with at least a first processor and a second processor, a non-volatile memory coupled to the first processor, and a processor bridge coupled between the first processor and the second processor, the non-volatile memory for storing a plurality of program codes comprising at least a first program code for the first processor and a second program code for the second processor, the memory sharing method comprising:

sending an access request from the second processor requesting data corresponding to the second program code to the processor bridge;

retrieving the access request from the processor bridge with the first processor;

fetching the data corresponding to the second program code from the non-volatile memory according to the access request with the first processor;

delivering the data corresponding to the second program code to the processor bridge; and

fetching the data from the processor bridge with the second processor.

12. The memory sharing method of claim 11 further comprising executing the first program code directly from the non-volatile memory with the first processor.

13. The memory sharing method of claim 11, wherein the plurality of processors further comprise a third processor being coupled to the processor bridge, the non-volatile memory is further for storing a third program code for the third processor, the method further comprising:

sending a second access request by the third processor requesting second data corresponding to the third program code to the processor bridge;

retrieving the second access request with the first processor from the processor bridge;

fetching the second data from the third program code in the non-volatile memory according to the second access request;

delivering the second data to the processor bridge; and

fetching the second data from the processor bridge by the third processor.

14. The memory sharing method of claim 13 further comprising:

executing the second program code with the second processor after the data corresponding to the second program code is fetched from the processor bridge; and

executing the third program code with the third processor after the second data corresponding to the third program code is fetched from the processor bridge.

15. The memory sharing method of claim 14, wherein the second processor is coupled to a first random access memory (RAM) module, and the third processor is coupled to a second RAM module, the method further comprising:

storing the second program code into the first RAM module after the data corresponding to the second program code is fetched from the processor bridge by the second processor;

executing the second program code from the first RAM module with the second processor;

storing the third program code into the second RAM module after the second data corresponding to the third program code is fetched from the processor bridge by the third processor; and

executing the third program code from the second RAM module by the third processor.

16. The memory sharing method of claim 15 further comprising:

performing a first program code transfer operation with the second processor by sending a plurality of access requests to the processor bridge to thereby completely obtain the second program code from the non-volatile memory;

completely storing the second program code into the first RAM module prior to executing the second program code from the first RAM module;

performing a second program code transfer operation with the third processor by sending a plurality of second access requests to the processor bridge to thereby completely obtain the third program code from the non-volatile memory; and

completely storing the third program code into the second RAM module prior to executing the third program code from the second RAM module.

17. The memory sharing method of claim 16 further comprising:

performing the first program code transfer operation immediately upon system startup;

executing the second program code after completion of the first program code transfer operation;

performing the second program code transfer operation immediately upon system startup; and

executing the third program code after completion of the second program code transfer operation.

18. The memory sharing method of claim 13 further comprising:

sending a first write request from the second processor to the processor bridge;

sending a second write request from the third processor to the processor bridge;

retrieving the first write request from the processor bridge by the first processor and storing a first write data in the non-volatile memory at a first write address according to the first write request; and

retrieving the second write request from the processor bridge by the first processor and storing second write data in the non-volatile memory at a second write address according to the second write request;

wherein the first write request comprises the first write data and the first write address for the first write data to be stored in the non-volatile memory, and the second write request comprises the second write data and the second write address for the second write data to be stored in the non-volatile memory.

19. The memory sharing method of claim 13 further comprising:

approving the access request only if the access request requests data from the second program code;

approving the second access request only if the second access request requests second data from the third program code;

fetching the data from the second program code in the non-volatile memory using the first processor according to the access request if the access request is approved; and

fetching the second data from the third program code in the non-volatile memory using the first processor according to the second access request if the second access request is approved.

20. The memory sharing method of claim 11 further comprising:

dividing the non-volatile memory into sections according to a number of processors in the multiple processor system; and

storing program code or data corresponding to a particular processor into a section of the non-volatile memory corresponding to the particular processor.