Semiconductor data processing device and data processing system

• US 7,447,932 B2
• Filed: 02/23/2007
• Issued: 11/04/2008
• Est. Priority Date: 11/22/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Semiconductor Kyushu Yamaguchi Company Limited (Renesas Electronics Corporation)
• Original Assignee: Renesas Northern Japan Semiconductor Incorporated (Hitachi High- Tech Corporation), Hitachi Device Engineering Co., Ltd. (Japan Display Incorporated), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamaguchi, Wataru, Ichien, Toru, Sasakawa, Masae, Wakabayashi, Mamoru
• Primary Examiner(s): Perveen; Rehana
• Assistant Examiner(s): Yanchus, III; Paul B
• Application Number:
  US11/709,777
• Publication Number:
  US 20070150768A1
• Time in Patent Office: 620 Days
• Field of Search: 713/400, 710/65, 710/66, 710/306, 710/307
• US Class Current: 713/400
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.

Claims

1. A semiconductor data processing device, comprising:

a first peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a second peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a data transfer controller capable of controlling data transfer between the first and the second peripheral circuits and that inputs and outputs data in parallel in units of 2n bits;

a 2n-bit first data bus coupled to the data transfer controller;

a 2n-bit second data bus coupled to the first and the second peripheral circuits;

a bus controller for connecting said first data bus to said second data bus; and

a central processing unit that processes parallel data in units of n bits or less, coupled to one of a lower and an upper part of said first data bus,

wherein the bus controller fixes the correspondence between each signal line of the second bus and a bit position of access data and varies the correspondence between each signal line of the first data bus and bit positions of the access data according to access data size.

2. A semiconductor data processing device according to claim 1,

wherein the first peripheral circuit comprises a USB controller.

3. A semiconductor data processing device according to claim 2, wherein the second peripheral circuit comprises a memory card controller.

4. A semiconductor data processing device according to claim 1,

wherein the second peripheral circuit comprises a memory card controller.

5. A semiconductor data processing device according to claim 1,

wherein the semiconductor data processing device is located on one semiconductor chip.

6. A single chip data processing device, comprising:

a first peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a second peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a 2n-bit first data bus;

a 2n-bit second data bus;

a data transfer controller that inputs and outputs data in parallel in units of 2n bits and is capable of controlling data transfer between the first peripheral circuit and the second peripheral circuit;

a bus controller coupled to the 2n-bit first data bus and to the 2n-bit second data bus; and

a central processing unit that processes parallel data in units of n bits or less, and is coupled to one of

a lower and an upper part of the 2n-bit first data bus,

wherein the first and the second peripheral circuits are coupled to the 2n-bit second data bus, and

wherein the bus controller fixes the correspondence between each signal line of the 2n-bit second bus and a bit position of access data and varies the correspondence between each signal line of the 2n-bit first data bus and bit positions of the access data according to access data size.

7. A single chip data processing device according to claim 6,

wherein the first peripheral circuit comprises a USB controller.

8. A single chip data processing device according to claim 7,

wherein the second peripheral circuit comprises a memory card controller.

9. A single chip data processing device according to claim 6,

wherein the second peripheral circuit comprises a memory card controller.

10. A single chip data processing device according to claim 6,

wherein the single chip data processing device is contained on a semiconductor substrate.

11. A semiconductor data processing device, comprising:

a first peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a second peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a direct memory access controller capable of controlling data transfer between the first and the second peripheral circuits and that inputs and outputs data in parallel in units of 2n bits;

a 2n-bit first data bus coupled to the data transfer controller;

a 2n-bit second data bus coupled to the first and the second peripheral circuit, respectively;

a bus controller for connecting said first data bus to said second data bus; and

a central processing unit that processes parallel data in units of n bits or less, coupled to one of a lower and an upper part of said first data bus,

wherein the bus controller fixes the correspondence between each signal line of the second bus and a bit position of access data and varies the correspondence between each signal line of the first data bus and bit positions of the access data according to access data size.

12. A semiconductor data processing device, comprising:

a first peripheral circuit that inputs and outputs data in units of n bits;

a second peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a data transfer controller capable of controlling data transfer between the first and the second peripheral circuits and that inputs and outputs data in parallel in units of 2n bits;

a 2n-bit first data bus coupled to the data transfer controller;

a 2n-bit second data bus coupled to the first and the second peripheral circuits;

a bus controller for connecting said first data bus to said second data bus; and

a central processing unit that processes parallel data in units of n bits or less, coupled to one of a lower and an upper part of said first data bus,

wherein the bus controller fixes the correspondence between each signal line of the second bus and a bit position of access data of the second peripheral circuit and varies the correspondence between each signal line of the second data bus and bit positions of the access data of the first peripheral circuit according to access data size and varies the correspondence between each signal line of the first data bus and bit positions of the access data according to access data size.

13. A semiconductor data processing device, comprising:

a first peripheral circuit that inputs and outputs data in units of n bits;

a second peripheral circuit that inputs and outputs parallel data in units of 2n bits;

a data transfer controller capable of controlling data transfer between the first and the second peripheral circuits and that inputs and outputs data in parallel in units of 2n bits;

a 2n-bit first data bus coupled to the data transfer controller;

a 2n-bit second data bus coupled to the first and the second peripheral circuits;

a bus controller for connecting said first data bus to said second data bus; and

a central processing unit that processes parallel data in units of n bits or less, coupled to one of a lower and an upper part of said first data bus,

wherein the bus controller fixes the correspondence between each signal line of the second bus and a bit position of access data of the first peripheral circuit and varies the correspondence between each signal line of the second data bus and bit positions of the access data of the second peripheral circuit according to access data size and varies the correspondence between each signal line of the first data bus and bit positions of the access data according to access data size.