Inversion of scan clock for scan cells

• US 7,447,961 B2
• Filed: 07/29/2004
• Issued: 11/04/2008
• Est. Priority Date: 07/29/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Tan, Teck Wee Patrick
• Primary Examiner(s): Louis-Jacques; Jacques
• Assistant Examiner(s): Tabone, Jr.; John J.
• Application Number:
  US10/903,971
• Publication Number:
  US 20060026473A1
• Time in Patent Office: 1,559 Days
• Field of Search: 714/726, 714/729, 714/731
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A scan clock source, coupled to the scan chain, generates a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells. The first and the second clock signals have an inverted relationship.

Claims

1. An apparatus, comprising:

a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain; and

a scan clock source, coupled to the scan chain, to provide a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells, where the scan clock source selectively inverts the first and the second scan clock signals based on an operating mode and respective flip-flop arrangements of the first and second clock domains,

wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

2. The apparatus according to claim 1, further comprising an original clock source, coupled to the scan clock source, to generate an original clock signal;

and wherein the scan clock source is operable to generate the first and the second scan clock signals in response to the original clock signal.

3. The apparatus according to claim 2, wherein each of the first and second pluralities of scan cells includes a flip-flop;

and the flip-flops of the second plurality of scan cells are operable to be triggered prior to the flip-flops of the first plurality of scan cells.

4. The apparatus according to claim 3, wherein each of the first and second pluralities of scan cells includes a positive edge-triggered flip-flop;

and the first scan clock signal is inverted relative to the original clock signal.

5. The apparatus according to claim 3, wherein each of the first and second pluralities of scan cells includes a negative edge-triggered flip-flop;

and the second scan clock signal is inverted relative to the original clock signal.

6. The apparatus according to claim 2, wherein a first scan cell at a beginning of the scan chain is operable to receive a scan-in signal in response to the first scan clock signal and a second scan cell at an end of the scan chain is operable to generate a scan-out signal in response to the second scan clock signal.

7. The apparatus according to claim 2, wherein the first and the second, clock signals have the same frequency.

8. The apparatus according to claim 2, further comprising a plurality of combination logic circuits;

and wherein each of the plurality of combination logic circuits includes an input coupled to a first scan cell of the first and second pluralities of scan cells and an output coupled to a second scan cell of the first and second pluralities of scan cells during a normal mode of operation wherein the first plurality of scan cells are clocked by a first system clock signal in the first clock domain and the second plurality of scan cells are clocked by a second system clock in the second clock domain; and

the first scan cell includes an output coupled to an input of the second scan cell during a scan mode of operation wherein the first plurality of scan cells are clocked by the first scan clock signal and the second plurality of scan cells are clocked by the second scan clock signal.

9. The apparatus according to claim 8, wherein the first and the second scan clock signals have the same frequency and the first and the second system clock signals have different frequencies.

10. The apparatus according to claim 2, wherein a clock crossing is defined between the first and the second clock domains and the scan-chain is disposed in traversing relationship to the clock crossing.

11. The apparatus according to claim 2, wherein the scan chain comprises a plurality of scan chains.

12. A method comprising:

generating a first scan clock signal to clock a first plurality of scan cells of a scan chain in a first clock domain;

generating a second scan clock signal to clock a second plurality of scan cells of the scan chain in a second clock domain; and

selectively inverting the first and the second scan clock signals based on an operating mode and respective flip-flop arrangements of the first and second clock domains,

wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

13. The method according to claim 12, further comprising generating the first and the second clock signals from a common original clock signal;

and wherein the inverting of the selected one of the first and the second scan clock signals includes inverting the selected one so that the selected one is 180 degrees out-of-phase with the original clock signal and a non-selected one is in-phase with the original clock signal.

14. The method according to claim 13, further comprising triggering the second plurality of scan cells with the second scan clock signal prior to triggering the first plurality of scan cells with the first scan clock signal.

15. The method according to claim 13, further comprising clocking a test pattern into a first scan cell of the first plurality of scan cells at a beginning of the scan chain in response to the first scan clock signal and clocking a system response out of a second scan cell of the second plurality of scan cells at an end of the scan chain in response to the second scan signal.

16. The method according to claim 14, wherein each of the first and second pluralities of scan cells includes a positive edge-triggered flip-flop;

and the inverting of the selected one of the first and the second scan clock signals includes inverting the first scan clock signal relative to the original clock signal.

17. The method according to claim 14, wherein each of the first and second pluralities of scan cells includes a negative edge-triggered flip-flop;

and the inverting of the selected one of the first and the second scan clock signals includes inverting the second scan clock signal relative to the original clock signal.

18. A method of designing a scan circuit, comprising:

arranging a first clock domain to be responsive to a first scan clock signal for clocking a first plurality of scan cells of a scan chain;

arranging a second clock domain to be responsive to a second scan clock signal for clocking a second plurality of scan cells of the scan chain;

positioning the first and the second clock domains adjacent to each other so as to provide a clock crossing with the scan chain traversing the clock crossing; and

selectively inverting the first and the second scan clock signals with a scan clock source based on an operating mode and respective flip-flop arrangements of the first and second clock domains so that the first and the second scan clock signals are out-of-phase with each other,

wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

19. The method according to claim 18, further comprising generating the first and the second scan clock signals in response to a single original clock signal.

20. The method according to claim 19, further comprising receiving a test pattern in response to the first scan clock signal at a first scan cell at the beginning of the scan chain;

and

clocking out a system response in response to the second scan signal at a second scan cell at the end of the scan chain.

21. The method according to claim 20, further comprising arranging the first and the second clock domains so that the second plurality of scan cells are triggered with the second scan clock signal prior to the first plurality of scan cells being triggered with the first scan clock signal.

22. The method according to claim 20, wherein each of the first and second pluralities of scan cells includes a positive edge-triggered flip-flop;

and the inverting a selected one of the first and the second scan clock signals includes inverting the first scan clock signal relative to the original clock signal.

23. The method according to claim 20, wherein each of the first and second pluralities of scan cells includes a negative edge-triggered flip-flop;

and the inverting a selected one of the first and the second scan clock signals includes inverting the second scan clock signal relative to the original clock signal.

24. A system, comprising:

an integrated circuit chip including a scan circuit having at least a first and a second clock domain and at least one scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain;

a scan clock source, coupled to the scan chain, to provide a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells, where the first and the second scan clock signals are selectively inverted based on an operating mode and respective flip-flop arrangements of the first and second clock domains so that the first and the second scan clock signals are 180 degrees out-of-phase to each other;

a bus with the integrated circuit chip coupled to the bus; and

a mass storage device coupled to the bus,

wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

25. The system according to claim 24, further comprising an original clock source, coupled to the scan clock source, to generate an original clock signal;

and wherein the scan clock source is operable to generate the first and the second scan clock signals in response to the original clock signal.

26. The system according to claim 25, wherein each of the first and second pluralities of scan cells include a flip-flop;

and the flip-flops of the second plurality of scan cells are operable to be triggered prior to the flip-flops of the first plurality of scan cells.

27. The system according to claim 25, wherein a first scan cell at a beginning of the at least one scan chain is operable to receive a scan-in signal in response to the first scan clock signal and a second scan cell at an end of the at least one scan chain is operable to generate a scan-out signal in response to the second scan clock signal.

28. The system according to claim 27, wherein each of the first and second pluralities of scan cells includes a positive edge-triggered flip-flop;

and the first scan clock signal is inverted relative to the original clock signal.

29. The system according to claim 27, wherein each of the first and second pluralities of scan cells includes a negative edge-triggered flip-flop;

and the second scan clock signal is inverted relative to the original clock signal.

30. The system according to claim 25, wherein the first and the second clock signals have the same frequency.