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Inversion of scan clock for scan cells

  • US 7,447,961 B2
  • Filed: 07/29/2004
  • Issued: 11/04/2008
  • Est. Priority Date: 07/29/2004
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain; and

    a scan clock source, coupled to the scan chain, to provide a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells, where the scan clock source selectively inverts the first and the second scan clock signals based on an operating mode and respective flip-flop arrangements of the first and second clock domains,wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.

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