Inversion of scan clock for scan cells
First Claim
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1. An apparatus, comprising:
- a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain; and
a scan clock source, coupled to the scan chain, to provide a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells, where the scan clock source selectively inverts the first and the second scan clock signals based on an operating mode and respective flip-flop arrangements of the first and second clock domains,wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells.
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Abstract
In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A scan clock source, coupled to the scan chain, generates a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells. The first and the second clock signals have an inverted relationship.
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Citations
30 Claims
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1. An apparatus, comprising:
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a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain; and a scan clock source, coupled to the scan chain, to provide a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells, where the scan clock source selectively inverts the first and the second scan clock signals based on an operating mode and respective flip-flop arrangements of the first and second clock domains, wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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generating a first scan clock signal to clock a first plurality of scan cells of a scan chain in a first clock domain; generating a second scan clock signal to clock a second plurality of scan cells of the scan chain in a second clock domain; and selectively inverting the first and the second scan clock signals based on an operating mode and respective flip-flop arrangements of the first and second clock domains, wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method of designing a scan circuit, comprising:
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arranging a first clock domain to be responsive to a first scan clock signal for clocking a first plurality of scan cells of a scan chain; arranging a second clock domain to be responsive to a second scan clock signal for clocking a second plurality of scan cells of the scan chain; positioning the first and the second clock domains adjacent to each other so as to provide a clock crossing with the scan chain traversing the clock crossing; and selectively inverting the first and the second scan clock signals with a scan clock source based on an operating mode and respective flip-flop arrangements of the first and second clock domains so that the first and the second scan clock signals are out-of-phase with each other, wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A system, comprising:
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an integrated circuit chip including a scan circuit having at least a first and a second clock domain and at least one scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain; a scan clock source, coupled to the scan chain, to provide a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells, where the first and the second scan clock signals are selectively inverted based on an operating mode and respective flip-flop arrangements of the first and second clock domains so that the first and the second scan clock signals are 180 degrees out-of-phase to each other; a bus with the integrated circuit chip coupled to the bus; and a mass storage device coupled to the bus, wherein a last scan cell of the first plurality of scan cells is directly connected to a first scan cell of the second plurality of scan cells. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification