BCH forward error correction decoder

• US 7,447,982 B1
• Filed: 03/30/2001
• Issued: 11/04/2008
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.), Iconverse (InfoClarus, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Thurston, Andrew J.
• Primary Examiner(s): Louis-Jacques; Jacques
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US09/822,950
• Time in Patent Office: 2,776 Days
• Field of Search: 714/785, 714/774, 714/784, 714/753, 714/782, 714/781, 714/752, 714/751, 714/746, 341/94, 341/50, 709/226
• US Class Current: 714/785
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/158 Finite field arithmetic processing
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/6561 Parallelized implementations

Abstract

An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. If the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

Claims

1. A method of decoding an error-correction code in a data signal, comprising the steps of:

receiving the data signal at a decoding unit;

computing a plurality of syndromes associated with the data signal using the decoding unit;

extracting an error polynomial from the data signal, wherein the extracting comprises generating a plurality of minimum-degree polynomials based on no more than six equations using no more than two branch decisions; and

locating errors within the data signal using the error polynomial.

2. The method of claim 1 wherein said extracting step extracts the error polynomial in no more than 12 clock cycles.

3. The method of claim 1 wherein said extracting step includes the step of controlling a plurality of Galois field multiply accumulators using a state machine.

4. The method of claim 3 wherein each of the plurality of Galois field multiply accumulators represents a different power of the error polynomial.

5. The method of claim 1 wherein said computing, extracting, and locating steps use a Bose-Chaudhuri-Hocquenghem (BCH) code.

6. The method of claim 1 wherein said computing steps computes 2t syndromes, where t is a number of correctable errors which the error-correcting code can correct.

7. The method of claim 1 wherein said computing step uses a linear feedback register to compute the syndromes.

8. The method of claim 1 wherein said computing step includes the steps of:

dividing a received code word in the data signal by a minimal Galois polynomial; and

evaluating a remainder from said dividing step.

9. The method of claim 1 wherein said extracting step generates the error polynomial based on the following six equations:

d₀=S₁, 

 

(1)

d₁=S₃+S₁S₂, 

 

(2)

σ

¹(X)=1+S₁X, 

 

(3)

if (d₁=0) then σ

²(X)=σ

¹(X)

else if (d₀=0) then σ

²(X)=q₀σ

¹(X)+d₁X³

else σ

²(X)=q₀σ

¹(X)+d₁X², 

 

(4)

d₂=S₅σ

₀+S₄σ

₁+S₃σ

₂+S₂σ

₃, and 

 

(5)

if (d₂=0) then σ

³(X)=σ

²(X)

else σ

³(X)=q₁σ

¹(X)+d₁X³, 

 

(6)

where S_i are the syndromes, σ

ⁱ are the minimum-degree polynomials, σ

_i are four coefficients for σ

²(X), d₀-d₂ are correction factors, q₀-q₁ are additional correction factors, q₀ is equal to d₀ unless d₀ is zero, when q₀ is 1, and q₁ is equal to d₁ unless d₁ is zero, when q₁=q₀.

10. The method of claim 1 wherein said extracting step includes the step of calculating correction terms using four Galois field multiply accumulators.

11. The method of claim 1 wherein said locating step locates the errors by determining roots of the error polynomial which correspond to error locations.

12. The method of claim 11 wherein said locating step uses Chien'"'"'s algorithm to search for the error location numbers.

13. The method of claim 1, wherein said extracting comprises using a non-iterative algorithm to generate the error polynomial from the data signal based on no more than six equations having no more than two branch decisions.

14. A method of determining an error polynomial for decoding a Bose-Chaudhuri-Hocquenghem (BCH) code, comprising the steps of:

computing a plurality of syndromes associated with a data signal having a BCH code embedded therein;

feeding the syndromes to a plurality of Galois field multiply accumulators;

calculating a plurality of minimum-degree polynomials associated with the BCH code, using the Galois field multiply accumulators; and

generating an error polynomial based on the minimum-degree polynomials, said calculating and generating steps extracting the error polynomial in no more than 12 clock cycles.

15. The method of claim 14 wherein said calculating step includes the step of calculating a plurality of coefficients of at least one of the minimum-degree polynomials.

16. The method of claim 14 wherein said calculating step includes the step of computing a first correction term using at least one of the Galois field multiply accumulators, the first correction term being equal to a first one of the syndromes.

17. The method of claim 16 wherein said calculating step includes the step of computing a second correction term using at least one of the Galois field multiply accumulators, the second correction term being equal to the sum of a product of the first syndrome with a second one of the syndromes, and a third one of the syndromes.

18. The method of claim 16 wherein said step of computing the first correction term includes the step of operating the at least one Galois field multiply accumulator in a pass-through mode.

19. The method of claim 14 wherein:

the BCH code is a triple-error correcting code; and

said calculating step calculates at least three minimum-degree polynomials.

20. The method of claim 19 wherein said calculating step further includes the steps of:

computing a first correction term using at least one of the Galois field multiply accumulators, the first correction term being equal to a first one of the syndromes;

computing a second correction term using at least one of the Galois field multiply accumulators, the second correction term being equal to the sum of a product of the first syndrome with a second one of the syndromes, and a third one of the syndromes; and

computing a third correction term using at least one of the Galois field multiply accumulators, the third correction term being based in part on coefficients of at least one of the minimum-degree polynomials.

21. The method of claim 20 wherein said calculating step includes the step of determining whether the second correction term is equal to zero.

22. The method of claim 21 wherein said calculating step equates a first one of the minimum-degree polynomials to a second one of the minimum-degree polynomials in response to a determination that the second correction term is equal to zero.

23. The method of claim 20 wherein said calculating step includes the step of determining whether the third correction term is equal to zero.

24. The method of claim 23 wherein said calculating step equates a first one of the minimum-degree polynomials to a second one of the minimum-degree polynomials in response to a determination that the third correction term is equal to zero.

25. The method of claim 19 wherein there are exactly four of the Galois field multiply accumulators, and said calculating step includes the step of controlling inputs to the Galois field multiply accumulators using a state machine.

26. A circuit for generating an error polynomial of a Bose-Chaudhuri-Hocquenghem (BCH) code, comprising:

a plurality of syndrome inputs;

a plurality of Galois field multiply accumulators; and

means for using said Galois field multiply accumulators to generate an error polynomial by generating a plurality of minimum-degree polynomials based on values provided at said syndrome inputs, by executing no more than six equations with two branch decisions.

27. The circuit of claim 26 wherein said using means includes a state machine which asserts control ports on the Galois field multiply accumulators to execute the equations.

28. The circuit of claim 26 wherein said using means computes a first correction term using at least one of the Galois field multiply accumulators, by assigning a value of a first one of the syndromes to the first correction term.

29. The circuit of claim 28 wherein said using means further computes a second correction term using at least one of the Galois field multiply accumulators, the second correction term being equal to the sum of a product of the first syndrome with a second one of the syndromes, and a third one of the syndromes.

30. The circuit of claim 28 wherein said using means computes the first correction term by operating at least one Galois field multiply accumulator in a pass-through mode.

31. The circuit of claim 26 wherein said using means uses the Galois field multiply accumulators to calculate a plurality of coefficients of at least one of the minimum-degree polynomials.

32. The circuit of claim 26 wherein:

the BCH code is a triple-error correcting code; and

said using means uses the Galois field multiply accumulators to calculate at least three minimum-degree polynomials.

33. The circuit of claim 26 wherein said using means uses the Galois field multiply accumulators to:

compute a first correction term, by assigning a value of a first one of the syndromes to the first correction term;

compute a second correction term, the second correction term being equal to the sum of a product of the first syndrome with a second one of the syndromes, and a third one of the syndromes; and

compute a third correction term, the third correction term being based in part on coefficients of at least one of the minimum-degree polynomials.

34. The circuit of claim 33 wherein said using means includes means for determining whether the second correction term is equal to zero.

35. The circuit of claim 34 wherein said using means equates a first one of the minimum-degree polynomials to a second one of the minimum-degree polynomials in response to a determination that the second correction term is equal to zero.

36. The circuit of claim 33 wherein said using means includes means for determining whether the third correction term is equal to zero.

37. The circuit of claim 36 wherein said using means equates a first one of the minimum-degree polynomials to a second one of the minimum-degree polynomials in response to a determination that the third correction term is equal to zero.

38. A decoder circuit comprising:

a plurality of Galois field multiply accumulators; and

a state machine programmed to use said Galois field multiply accumulators to generate an error polynomial based on the following six equations;

d₀=S₁, 

 

(1)

d₁=S₃+S₁S₂, 

 

(2)

σ

¹(X)=1+S₁X, 

 

(3)

if (d₁=0) then σ

²(X)=σ

¹(X)

else if (d₀=0) then σ

²(X)=q₀σ

¹(X)+d₁X³

else σ

²(X)=q₀σ

¹(X)+d₁X², 

 

(4)

d₂=S₅σ

₀+S₄σ

₁+S₃σ

₂+S₂σ

₃, and 

 

(5)

if (d₂=0) then σ

³(X)=σ

²(X)

else σ

³(X)=q₁σ

¹(X)+d₁X³, 

 

(6)

where S_i are error syndromes, σ

ⁱ are minimum-degree polynomials, σ

_i are four coefficients for σ

²(X), d₀-d₂ are correction factors, q₀-q₁ are additional correction factors, q₀ is equal to d₀ unless d₀ is zero, when q₀ is 1, and q₁ is equal to d₁ unless d₁ is zero, when q₁=q₀.

39. The decoder circuit of claim 38 wherein each of the Galois field multiply accumulators represents a different power of the error polynomial.

40. The decoder circuit of claim 38 wherein said state machine is programmed to operate a selected one or more of said Galois field multiply accumulators in a pass-through mode.

41. The decoder circuit of claim 38 wherein said state machine and said Galois field multiply accumulators are formed in a common application-specific integrated circuit.

42. The decoder circuit of claim 38 wherein:

the BCH code is a triple-error correcting code; and

there are exactly four of said Galois field multiply accumulators.

43. The decoder circuit of claim 42 wherein equation (1) is performed using a first one of said Galois field multiply accumulators.

44. The decoder circuit of claim 43 wherein equation (2) is performed using said first Galois field multiply accumulator and a second one of said Galois field multiply accumulators.

45. The decoder circuit of claim 44 wherein equation (3) is performed using said first and second Galois field multiply accumulators.

46. The decoder circuit of claim 38 wherein:

at least one of said Galois field multiply accumulators has a first multiplexer whose output is coupled to a first input of a Galois field multiplier, a second multiplexer whose output is coupled to a second input of said Galois field multiplier, and a third multiplexer whose output is coupled to a first input of a Galois field adder, wherein an output of said Galois field multiplier is further coupled to a second input of said Galois field adder;

and

said state machine controls respective select lines for each of said multiplexers.

47. The decoder circuit of claim 46 further comprising means for determining when an output of said Galois field adder is equal to zero.

48. An OC-192 input/output card comprising:

four OC-48 processors; and

an OC-192 front-end application-specific integrated circuit (ASIC) connected to said four OC-48 processors, said OC-192 front-end ASIC having means for de-interleaving an OC-192 signal to create four OC-48 signals, and means for decoding error-correction codes embedded in each of the four OC-48 signals, said decoding means including means for generating an error polynomial associated with a given one of the error-correction codes in no more than 12 clock cycles, wherein said decoding means uses a non-iterative algorithm to generate the error polynomial based on a plurality of minimum-degree polynomials.

49. The OC-192 input/output card of claim 48 wherein said decoding means includes a plurality of Galois field multiply accumulators.

50. The OC-192 input/output card of claim 49 wherein said decoding means further includes a state machine controlling said Galois field multiply accumulators.

51. The OC-192 input/output card of claim 49 wherein said decoding means uses said Galois field multiply accumulators to generate an error polynomial for a Bose-Chaudhuri-Hocquenghem (BCH) triple-error correcting code.

52. The OC-192 input/output card of claim 51 wherein said decoding means includes no more than four of said Galois field multiply accumulators.

53. The OC-192 input/output card of claim 51 wherein said decoding means includes means for computing a plurality of BCH syndromes which are used by said Galois field multiply accumulators to generate the error polynomial.

54. The OC-192 input/output card of claim 48 wherein said decoding means locates errors within the data signal by applying Chien'"'"'s algorithm to the error polynomial to search for error location numbers.