Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch

• US 7,449,354 B2
• Filed: 01/05/2006
• Issued: 11/11/2008
• Est. Priority Date: 01/05/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce Douglas, Kraft, Nathan Lawrence, Grebs, Thomas E., Ridley, Rodney S.
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US11/327,657
• Publication Number:
  US 20070155104A1
• Time in Patent Office: 1,041 Days
• Field of Search: 438/39, 438/40, 438/42, 438/43, 438/128, 438/259, 438/270, 438/942, 438/FOR.100, 438/FOR.208, 438/FOR.240, 257/E29.201, 257/E29.257, 257/E29.26
• US Class Current: 438/39
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer

Abstract

A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.

Claims

1. A method of forming a trench-gated field effect transistor (FET), comprising:

using one mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.

2. The method of claim 1 further comprising:

forming a recessed layer inside the plurality of active gate trenches and inside the at least one gate runner trench using CMP.

3. The method of claim 2 wherein the recessed layer is a thick bottom dielectric (TBD) formed along a bottom portion of the plurality of active gate trenches and the gate runner trench.

4. The method of claim 2 wherein the recessed layer is a polysilicon layer forming a gate electrode in each of the plurality of active gate trenches and a gate runner in the gate runner trench, wherein the gate electrode and the gate runner are contiguous.

5. The method of claim 2 further comprising:

forming a CMP stop layer prior to the defining and simultaneously forming step;

forming a first layer filling the plurality of active gate trenches and extending over mesa regions adjacent the plurality of active gate trenches; and

polishing back the first layer until the CMP stop layer over the mesa regions is reached;

recessing the polished back first layer into the plurality of active gate trenches to a predetermined depth.

6. The method of claim 5 wherein the recessed layer is a polysilicon layer and the CMP stop layer is a non-conducting layer.

7. The method of claim 1 further comprising:

forming a recessed gate electrode in each of the plurality of active gate trenches and a recessed gate runner in the at least one gate runner trench; and

forming a dielectric cap over the gate electrode in each of the plurality of active gate trenches and over the gate runner in the gate runner trench using CMP.

8. The method of claim 7 further comprising:

after the step of forming a recessed gate electrode, forming a first dielectric layer filling the plurality of active gate trenches and the gate runner trench and extending over mesa regions adjacent the plurality of active gate trenches; and

polishing back the first dielectric layer until a predesignated CMP stop layer is reached, thereby forming the dielectric cap over each gate electrode and the gate runner.

9. The method of claim 8 wherein the predesignated CMP stop layer is the silicon region.

10. The method of claim 8 wherein the predesignated CMP stop layer is a nitride layer formed prior to the step of the forming a first dielectric layer.

11. The method of claim 8 further comprising:

forming a contact opening in the dielectric cap over the recessed gate runner; and

forming an interconnect layer contacting the gate runner through the contact opening.

12. The method of claim 1 wherein the plurality of active gate trenches extend perpendicularly to the at least one gate runner trench.

13. The method of claim 1 wherein the one mask is used to form at least one termination trench in a termination region of the silicon region simultaneously with the plurality of active gate trenches and the at least one gate runner trench.

14. The method of claim 1 further comprising:

forming a thick bottom dielectric (TBD) along a bottom portion of the plurality of active gate trenches and the at least one gate runner trench using CMP.

15. The method of claim 14 wherein the TBD forming step comprises:

forming a dielectric layer filling the plurality of active gate trenches and extending into the gate runner trench and over mesa regions adjacent the plurality of active gate trenches;

polishing back the dielectric layer until a predesignated CMP stop layer extending over the mesa regions is reached; and

recessing the polished back dielectric layer only into the plurality of active gate trenches to a predetermined depth.

16. The method of claim 15 wherein the predesignated CMP stop layer is the silicon region.

17. The method of claim 15 wherein the predesignated CMP stop layer is a silicon layer formed after the defining and simultaneously forming step.

18. The method of claim 15 wherein the predesignated CMP stop layer is a nitride layer in the one mask.

19. The method of claim 1 further comprising:

forming a polysilicon layer filling the plurality of active gate trenches and the gate runner trench and extending over mesa regions adjacent the plurality of active gate trenches;

polishing back the polysilicon layer until a predesignated CMP stop layer extending over the mesa regions is reached; and

recessing the polished back polysilicon layer into the plurality of active gate trenches and the at least one gate runner trench to a predetermined depth, thereby forming a recessed gate electrode in each of the plurality of active gate trenches and a recessed gate runner in the gate runner trench.

20. The method of claim 19 wherein the predesignated CMP stop layer is a non-conducting layer formed prior to the step of forming a polysilicon layer.

21. The method of claim 20 wherein the non-conducting layer is a gate dielectric.

22. The method of claim 20 wherein the non-conducting layer is a combination of a gate dielectric and the one mask.

23. The method of claim 20 wherein the non-conducting layer is a nitride layer in the one mask.

24. The method of claim 19 further comprising:

prior to the polysilicon layer forming step, forming a thick bottom dielectric (TBD) along a bottom portion of the plurality of active gate trenches and the at least one gate runner trench using CMP.

25. The method of claim 24 wherein the TBD forming step comprises:

forming a first dielectric layer filling the plurality of active gate trenches and extending into the gate runner trench and over mesa regions adjacent the plurality of active gate trenches;

polishing back the first dielectric layer until a predesignated CMP stop layer extending over the mesa regions is reached; and

recessing the polished back first dielectric layer only into the plurality of active gate trenches to a predetermined depth.

26. The method of claim 25 wherein the predesignated CMP stop layer in the step of polishing back the first dielectric layer is the silicon region.

27. The method of claim 25 wherein the predesignated CMP stop layer in the step of polishing back the first dielectric layer is a silicon layer formed after the defining and simultaneously forming step.

28. The method of claim 25 wherein the predesignated CMP stop layer in the step of polishing back the first dielectric layer is a nitride layer in the one mask.

29. The method of claim 25 further comprising:

after the step of recessing the polished back polysilicon layer, forming a second dielectric layer filling the plurality of active gate trenches and the gate runner trench and extending over mesa regions adjacent the plurality of active gate trenches; and

polishing back the second dielectric layer until a predesignated CMP stop layer is reached, thereby forming a dielectric cap over each of the recessed gate electrodes and the recessed gate runner.

30. The method of claim 29 wherein the predesignated CMP stop layer in the step of forming a second dielectric layer is the silicon region.

31. The method of claim 29 wherein the predesignated CMP stop layer in the step of forming a second dielectric layer is a nitride layer.

32. The method of claim 31 wherein the one mask comprises the nitride layer.

33. The method of claim 29 further comprising:

forming a contact opening in the dielectric cap over the recessed gate runner; and

forming an interconnect layer contacting the gate runner through the contact opening.

34. The method of claim 19 further comprising:

after the step of recessing the polished back polysilicon layer, forming a dielectric layer filling the plurality of active gate trenches and the gate runner trench and extending over mesa regions adjacent the plurality of active gate trenches; and

polishing back the dielectric layer until a predesignated CMP stop layer is reached, thereby forming a dielectric cap over each of the recessed gate electrodes and the recessed gate runner.

35. The method of claim 34 wherein the predesignated CMP stop layer in the step of forming a dielectric layer is the silicon region.

36. The method of claim 34 wherein the predesignated CMP stop layer in the step of forming a dielectric layer is a nitride layer.

37. The method of claim 36 wherein the one mask comprises the nitride layer.

38. The method of claim 34 further comprising:

forming a contact opening in the dielectric cap over the recessed gate runner; and

forming an interconnect layer contacting the gate runner through the contact opening.

39. The method of claim 19 wherein the silicon region has a first conductivity type, the method further comprising:

forming a well region of a second conductivity type in the silicon region;

forming source regions of the first conductivity type in the well region; and

forming a first metal layer electrically contacting the well region and the source regions, and a second metal layer contacting the recessed gate runner.