Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

• US 7,449,358 B2
• Filed: 03/29/2005
• Issued: 11/11/2008
• Est. Priority Date: 12/07/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Patel, Satyadev R., Huibers, Andrew G., Chiang, Steve S.
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Thomas; Toniae M.
• Application Number:
  US11/093,927
• Publication Number:
  US 20050170614A1
• Time in Patent Office: 1,323 Days
• Field of Search: 438/25, 438/28, 438/58, 438 67- 68, 438/108, 438/113, 438/458, 438/118
• US Class Current: 438/58
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00214 Processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: B81C 1/00904 Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01054 : Xenon [Xe]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Claims

1. A method for making a plurality of spatial light modulators, comprising:

providing a transparent wafer and a semiconductor wafer;

depositing and patterning sacrificial and structural materials on the semiconductor wafer to form a plurality of micromirrors within a plurality of rectangular micromirror arrays;

removing the sacrificial material to release the plurality of micromirrors in the plurality of micromirror arrays;

providing a getter for each micromirror array such that after bonding a getter is provided proximate to each array;

bonding the transparent wafer and semiconductor wafer together to form a wafer assembly with a spacer layer therebetween so as to define gaps in which the micromirror arrays are each disposed; and

singulating the wafer assembly into individual spatial light modulators.

2. The method of claim 1, wherein the spacer layer comprises microfabricated spacers.

3. The method of claim 1, wherein the spacer layer comprises pillars provided at the side of each micromirror array.

4. The method of claim 1, wherein the spacer layer comprises spacers mixed into an adhesive and deposited along with the adhesive.

5. The method of claim 4, wherein the spacers are balls or rods and the adhesive is epoxy.

6. The method of claim 1, wherein the spacer layer comprises one or more intermediate wafers with open areas corresponding to each micromirror array.

7. The method of claim 1, wherein the bonding of the transparent and semiconductor substrates comprises aligning and tacking the substrates together.

8. The method of claim 7, wherein the bonding of the transparent and semiconductor substrates further comprises pressing the tacked substrates in a press.

9. The method of claim 8, wherein the press is a thermal press.

10. The method of claim 8, wherein the press is a UV press.

11. The method of claim 1, wherein the singulating of the wafer assembly comprises singulating the transparent and semiconductor wafers into spatial light modulators where the singulated spatial light modulator have a transparent die portion bonded to a semiconductor die portion, and wherein an edge of the transparent die portion is offset from an edge of the semiconductor die portion.

12. The method of claim 11, wherein an area on the semiconductor die portion is exposed for testing the micromirrors after singulating.

13. The method of claim 11, wherein an area on the semiconductor die portion extends out from under the transparent die portion and comprises a bond pad area with bond wires attached thereto.

14. The method of claim 13, wherein the transparent die portion is quartz.

15. The method of claim 13, wherein the transparent die portion is glass.

16. The method of claim 15, wherein the semiconductor die portion is silicon.

17. The method of claim 16, wherein the number of micromirrors in each micromirror array is from 6,000 to about 6 million.

18. The method of claim 17, wherein the wafer assembly is singulated into individual spatial light modulators by scribing and breaking.

19. The method of claim 17, wherein the singulation of the wafer assembly into individual spatial light modulators comprises sawing.

20. The method of claim 1, wherein the bonding of the transparent wafer to the semiconductor wafer comprises aligning fiducials on the wafers.

21. The method of claim 20, wherein the alignment comprises automated pattern recognition.

22. The method of claim 1, wherein the transparent wafer and substrate wafer are aligned with the aid of a video camera with lens magnification.

23. The method of claim 1, wherein a spatial light modulator formed after singulation is placed within a projection display and where the micromirrors in the spatial light modulator correspond to pixels of the projection display.

24. The method of claim 17, wherein the spacer layer comprises a spacing wafer between the first and second wafers.

25. The method of claim 1, wherein the spacer layer is provide by providing microfabricated spacers on one or both of the transparent and semiconductor wafers prior to bonding.

26. The method of claim 17, further comprising applying a stiction reducing agent to one or both wafers before or after bonding the two wafers together.

27. The method of claim 26, wherein the stiction reducing agent is applied before bonding the wafers together.

28. The method of claim 26, wherein the stiction reducing agent is applied after bonding the wafers together.

29. The method of claim 28, wherein the stiction reducing agent is applied before singulating the wafer assembly into individual spatial light modulators.

30. The method of claim 1, wherein the singulating of the wafer assembly comprises partially scribing or sawing the transparent wafer and semiconductor wafer, where scribing or sawing on one wafer is offset from scribing or sawing on the other wafer.

31. The method of claim 30, wherein the singulation further comprises breaking the wafer assembly along the scribe or saw lines.

32. The method of claim 17, wherein the singulation of the wafer assembly comprises sawing partially through each wafer followed by breaking along the sawed lines.

33. The method of claim 32, wherein the sawing is done in the presence of a high-pressure jet of water.

34. The method of claim 1, wherein the bonding comprises applying a sealant near the perimeter of each array on the wafer.

35. The method of claim 33, further comprising applying a sealant around the perimeter of at least one of the wafers.

36. The method of claim 1, wherein the transparent wafer and semiconductor wafer are bonded together with the gap therebetween being from 1 to 250 microns.

37. The method of claim 36, wherein the gap is from 1 to 100 microns.

38. The method of claim 36, wherein the spacer layer comprises glass or plastic spacers.

39. The method of claim 17, wherein circuitry and a plurality of electrodes are formed prior to forming the plurality of micromirrors, wherein the plurality of micromirrors is formed above the plurality of electrodes on the semiconductor wafer.

40. The method of claim 1, further comprising providing a getter on the transparent wafer or semiconductor wafer before bonding the wafers together into the wafer assembly.

41. The method of claim 1, wherein the getter is a molecular, hydrogen and/or particle getter.

42. The method of claim 1, wherein the getter is a particulate and moisture getter.

43. The method of claim 1, wherein the getter is capable of absorbing moisture.

44. The method of claim 40, wherein a light blocking mask is formed on the transparent wafer.

45. The method of claim 44, wherein when the wafer assembly is singulated into individual spatial light modulators, a light blocking mask is disposed on a transparent substrate within each spatial light modulator, the light blocking mask being formed as a rectangular frame around each micromirror array in each spatial light modulator.

46. The method of claim 1, further comprising a light blocking rectangular mask for each spatial light modulator after singulation.

47. The method of claim 1, further comprising depositing on the transparent wafer a light blocking mask on a side of the transparent wafer facing the micromirrors after wafer bonding, wherein the light blocking mask surrounds each micromirror array as a picture frame within each spatial light modulator after singulation.

48. The method of claim 1, further comprising packaging the spatial light modulators.

49. The method of claim 1, further comprising providing the semiconductor substrate of each spatial light modulator on a lower packaging substrate.

50. The method of claim 1, wherein the micromirrors have jagged or zig-zag edges.

51. The method of claim 1, wherein the bonding comprises aligning the wafers prior to bonding with an accuracy of 10 microns or less.

52. The method of claim 1, further comprising providing a getter prior to wafer bonding, and providing a stiction reducing agent after wafer bonding.

53. The method of claim 52, wherein the depositing and patterning of sacrificial and structural materials comprises depositing and patterning sacrificial material on the transparent or semiconductor substrate, and depositing and patterning structural material thereon so as to define micromirror plates and hinges for the plurality of micromirrors.

54. The method of claim 53, wherein the sacrificial material is amorphous silicon.

55. A method for making a plurality of spatial light modulators, comprising:

providing a transparent wafer and a semiconductor wafer;

forming a plurality of deflectable micromirrors within a plurality of rectangular micromirror arrays;

providing a getter for each micromirror array such that after bonding a getter is provided proximate to each array;

bonding the transparent wafer and semiconductor wafer together to form a wafer assembly with a spacer therebetween so as to define gaps in which the micromirror arrays are each disposed; and

singulating the wafer assembly into individual spatial light modulators.

56. The method of claim 55, further comprising providing a getter for each micromirror array on the transparent wafer or semiconductor wafer before bonding the transparent wafer to the semiconductor wafer.

57. The method of claim 55, further comprising providing a light blocking mask on the transparent wafer.

58. The method of claim 57, wherein when the wafer assembly is singulated into individual spatial light modulators, a light blocking mask is disposed on a transparent substrate within each spatial light modulator.

59. The method of claim 58, wherein the light blocking mask is formed as a rectangular frame around each micromirror array in each spatial light modulator after singulation.

60. The method of claim 55, wherein a stiction reducing agent is provided after wafer bonding.

61. The method of claim 60, wherein each spatial light modulator comprises a getter, stiction reducing agent and light blocking mask.

62. The method of claim 60, wherein singulation is performed such that an edge of the transparent substrate in each spatial light modulator is offset from an edge of the semiconductor substrate in each spatial light modulator.

63. The method of claim 62, wherein the transparent wafer is glass.

64. The method of claim 63, wherein the semiconductor wafer is silicon.

65. The method of claim 55, further comprising a packaging substrate, wherein the silicon substrate of each spatial light modulator is disposed on a corresponding packaging substrate.

66. The method of claim 62, wherein the offset edges of the glass and silicon substrates in each spatial light modulator results in an exposed area on the silicon substrate for testing.

67. The method of claim 66, wherein the exposed area further comprises bond wires bonded thereto.

68. The method of claim 55, wherein the spacer comprises one or more intermediate wafers with open areas bonded between the transparent wafer and the semiconductor wafer.

69. The method of claim 55, wherein the semiconductor wafer and the transparent wafer are aligned and pressed in a press.

70. The method of claim 55, wherein the transparent wafer is bonded to the semiconductor wafer with an adhesive.

71. The method of claim 70, wherein the adhesive is an epoxy.

72. The method of claim 55, wherein the number of micromirrors in each micromirror array is from 6,000 to about 6 million.

73. The method of claim 55, wherein the micromirrors are formed on the semiconductor substrate.

74. The method of claim 72, wherein the transparent wafer and semiconductor wafer are bonded together with the gap therebetween being from 1 to 250 microns.

75. The method of claim 55, wherein the getter is a moisture getter.

76. The method of claim 55, wherein the getter is a particle getter.

77. The method of claim 70, wherein the micromirrors are formed on the transparent wafer.

78. The method of claim 55, wherein the getter is a combination getter.