Method of ion implanting for tri-gate devices

• US 7,449,373 B2
• Filed: 03/31/2006
• Issued: 11/11/2008
• Est. Priority Date: 03/31/2006
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack T., Doyle, Brian S., Majumdar, Amlan, Datta, Suman
• Primary Examiner(s): Kebede; Brook
• Application Number:
  US11/394,614
• Publication Number:
  US 20070238273A1
• Time in Patent Office: 956 Days
• Field of Search: 438/149, 438/157, 438/197, 438/230, 438/231, 438/232, 438/302, 438/527, 438/142, 438/202, 257/412, 257/E21.345, 257/E21.442, 257/E27.112, 257/E29.275, 257/E21.618, 257/E21.633
• US Class Current: 438/149
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.

Claims

1. A method for fabricating a semiconductor device comprising:

ion implanting, a semiconductor fin disposed on a substrate, which fin is initially disposed along a Y-axis, extends above the substrate along a Z-axis, and has a gate structure transversing the fin along a X-axis, with ions of a first conductivity type to form spaced-apart tip source and drain regions in the fin along the Y-axis; and

ion implanting the semiconductor fin generally under the gate structure, with ions of a second conductivity type to form halo regions generally between the spaced-apart tip source and drain regions, the halo ion implanting occurring with the wafer twisted in the XY plane at a first acute angle, and tilted at a second acute angle in the YZ plane.

2. The method defined by claim 1, wherein the first acute angle is between approximately 10°

-45°

.

3. The method defined by claim 2, wherein the second acute angle is approximately 50°

-55°

.

4. The method defined by claim 3, wherein the halo implantation also occurs at the first and second acute angles after the substrate has been twisted approximately 180°

so as to implant under the gate structure from the opposite side.

5. The method defined by claim 4, wherein the second acute angle is approximately 50°

-55°

.

6. The method defined by claim 5, wherein the first acute angle is approximately 10°

-45°

.

7. The method defined by claim 6, wherein the fin comprises a monocrystalline silicon.

8. The method defined by claim 7, wherein the fin is implanted by the halo ion implantation to a dose of 1E12-1E13 atoms.

9. The method defined by claim 1, wherein the halo ion implantation occurs before the tip ion implantation.

10. A method of fabricating a semiconductor device comprising:

performing one of the following steps before the other;

ion implanting a semiconductor fin disposed on a substrate, which fin is initially disposed on a Y-axis, extends above the substrate on a Z-axis, and has a gate structure transversing the fin on a X-axis, with ions of a first conductivity type to form spaced-apart tip source and drain regions in the fin along the Y-axis, the tip ion implanting occurring with the wafer twisted by approximately 90° and

tilted at a first angle in the YZ plane; and

ion implanting the semiconductor fin generally under the gate structure, with ions of a second conductivity type to form halo regions, generally between the spaced-apart tip source and drain regions, the halo ion implanting occurring with the wafer twisted in the XY plane at plus and minus a second acute angle, and tilted at a third acute angle in the YZ plane.

11. The method defined by claim 10, wherein the halo implantation also occurs at plus and minus the second acute angle after the substrate has been twisted approximately 180°

so as to implant under the gate structure from the opposite side.

12. The method defined by claim 10, wherein the first acute angle is between approximately 50°

-55°

.

13. The method defined by claim 12, wherein the second acute angle is approximately between 10°

-45°

.

14. The method defined by claim 13, wherein the third acute angle is approximately between 50°

-55°

.

15. The method defined by claim 11, wherein the first and third acute angle is approximately between 50°

-55° and

the second acute angle is approximately between 10°

-45°

.

16. The method defined by claim 10, including forming spacers on the gate structure before the tip and halo implantations.

17. The method defined by claim 10, including forming spacers between the two implantation steps of claim 10.

18. The method defined by claim 10, wherein the substrate is a bulk silicon substrate.

19. The method defined by claim 10, wherein the substrate is a silicon-on-insulator (SOI) substrate.