Method for forming multiple doping level bipolar junctions transistors

• US 7,449,388 B2
• Filed: 07/18/2006
• Issued: 11/11/2008
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Carroll, Michael Scott, Key, Roger W., Lai, Thiet The, Hamad, Amal Ma, Kerr, Daniel Charles
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/458,270
• Publication Number:
  US 20060252215A1
• Time in Patent Office: 847 Days
• Field of Search: 438/309
• US Class Current: 438/309
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence

Abstract

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

Claims

1. A process for forming a bipolar junction transistor in a semiconductor substrate, the process comprising:

forming first doped tub regions of a first dopant type within the substrate, wherein the first doped tub regions are located within metal oxide semiconductor field effect transistor (MOSFET) regions;

using a first mask to form sinker regions of a second dopant type within the substrate, wherein at least a portion of the sinker regions are located within bipolar junction transistor (BJT) regions and a remaining portion of the sinker regions are located in the MOSFET regions adjacent the first doped tub regions;

using a second mask, and the second dopant type, to form first subcollectors within a portion of the BJT regions that include a portion of the sinker regions, and triple well regions within the MOSFET that electrically isolate the first doped tub regions, and the another mask covering a remaining portion of the sinker regions to prevent the remaining portion from being doped; and

forming gate structures over the MOSFET regions;

using a third mask to dope a portion of each of the first subcollectors, the remaining portions of the sinker regions, and source/drains regions in the first doped tub regions with the second dopant type; and

using a fourth mask to dope the remaining portions of the sinker regions to form second subcollectors and a portion of the first subcollector regions with the second dopant, such that the portion of the first subcollector regions has a dopant concentration different from a remaining portion of the first subcollector regions and the second subcollector regions.

2. The process of claim 1

wherein the first doped tub regions and the triple well regions and the gate structures cooperate to form a metal oxide semiconductor field effect transistors;

and

forming second structures associated with the doped sinker region and the subcollector region, wherein the second structures, the doped sinker region and the subcollector region cooperate to form the bipolar junction transistor.

3. The process of claim 2 wherein the gate structures are formed after concurrently forming the first subcollector regions and the triple well regions.

4. The process of claim 2 further comprising forming second metal oxide semiconductor field effect transistors of an opposite doping type from the first metal oxide semiconductor field effect transistors, wherein the first and the second metal oxide semiconductor field effect transistors form complimentary metal oxide semiconductor field effect transistors.

5. The process of claim 1 wherein the step of forming the first subcollector regions and the triple well regions comprises implanting dopants to form the subcollector region and the triple well region.

6. The process of claim 5 wherein the step of implanting dopants further comprises implanting phosphorous at about 1000 keV with a dose of about 2E13 per cubic cm.

7. The process of claim 1 further comprising forming material layers overlying the substrate and forming an emitter windows within one or more of the material layers, wherein the step of doping the portion of the subcollector region comprises doping the portion of the subcollector region through the emitter window.

8. The method of claim 7, further comprising forming a base in one or more of the BJT regions.

9. The method of claim 8 wherein at least three of the BJT'"'"'s have different breakdown characteristics during operation.