Power semiconductor module as H-bridge circuit and method for producing the same
First Claim
1. A power semiconductor module as H-bridge circuit comprising four power semiconductor chips and a semiconductor control chip, the semiconductor chips being arranged on three mutually separate large-area lead chip contact areas of a lead plane, having a centrally arranged lead chip contact area, on which the semiconductor control chip is arranged, and two laterally arranged lead chip contact areas, on each of which are arranged an n-channel power semiconductor chip as low-side switch and a p-channel power semiconductor chip as high-side switch, and the n-channel power semiconductor chips being jointly electrically connected to an earth potential and the p-channel power semiconductor chips being electrically connected to separate supply voltage sources.
1 Assignment
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Accused Products
Abstract
A power semiconductor module (41) as H-bridge circuit (42) has four power semiconductor chips (N1, N2, P1, P2) and a semiconductor control chip (IC). The semiconductor chips (N1, N2, P1, P2, IC) are arranged on three mutually separate large-area lead chip contact areas (43 to 45) of a lead plane (80). The semiconductor control chip (IC) is arranged on a centrally arranged lead chip contact area (45). An n-channel power semiconductor chip (N1, N2) as low-side switch (58, 59) and a p-channel power semiconductor chip (P1, P2) as high-side switch (48, 49) are in each case arranged on two laterally arranged lead chip contact areas (43, 44). The n-channel power semiconductor chips (N1, N2) are jointly at an earth potential (50) and the p-channel power semiconductor chips (P1, P2) are electrically connected to separate supply voltage sources (VS1, VS2).
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Citations
16 Claims
- 1. A power semiconductor module as H-bridge circuit comprising four power semiconductor chips and a semiconductor control chip, the semiconductor chips being arranged on three mutually separate large-area lead chip contact areas of a lead plane, having a centrally arranged lead chip contact area, on which the semiconductor control chip is arranged, and two laterally arranged lead chip contact areas, on each of which are arranged an n-channel power semiconductor chip as low-side switch and a p-channel power semiconductor chip as high-side switch, and the n-channel power semiconductor chips being jointly electrically connected to an earth potential and the p-channel power semiconductor chips being electrically connected to separate supply voltage sources.
Specification