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Wire bonded wafer level cavity package

  • US 7,449,779 B2
  • Filed: 12/30/2005
  • Issued: 11/11/2008
  • Est. Priority Date: 03/22/2005
  • Status: Expired due to Fees
First Claim
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1. A microelectronic device comprising:

  • (a) a chip having a front surface and a rear surface, said front surface including an active region and a plurality of contacts exposed at said front surface outside of said active region;

    (b) a lid overlaying said front surface of said chip, said lid having an outer surface, an inner surface, and edges bounding said lid, at least one of said edges including one or more outer portions and one or more recesses extending laterally inwardly from said outer portions, said recesses being formed by one or more surfaces oblique to said outer surface of said lid, said contacts being aligned with said recesses and exposed through said recesses.

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