VPA logic circuits

• US 7,449,915 B2
• Filed: 11/30/2006
• Issued: 11/11/2008
• Est. Priority Date: 06/30/2004
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Teig, Steven
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Crawford, Jason
• Application Number:
  US11/565,607
• Publication Number:
  US 20070241788A1
• Time in Patent Office: 712 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

Claims

1. An integrated circuit (“

IC”

) comprising;

a) a first logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set;

b) a second circuit communicatively coupled to the first logic circuit, the second circuit for supplying configuration data sets to the first logic circuit, the second circuit having a first set of input terminals;

c) a second set of input terminals for carrying data, wherein a plurality of the second set of input terminals overlap a plurality of the first set of input terminals; and

d) a via programmed structure comprising a set of vias and potential vias, wherein a plurality of vias in the via programmed structure connect the input terminals in the first set with the input terminals in the second set, wherein the IC receives a control signal, wherein the second set of input terminals receives at least a portion of said control signal.

2. The IC of claim 1, wherein said plurality of vias are programmably set to provide a particular configuration data set to the logic circuit.

3. The IC of claim 1, wherein the control signal is a clock signal.

4. The IC of claim 3 further comprising a sub-cycle signal generator that generates the control signal.

5. The IC of claim 1, wherein the second circuit is for supplying configuration data sets to the first logic circuit at a particular rate for at least a duration of time.

6. The IC of claim 1, wherein the second circuit receives configuration data through the via connections between the first and second sets of input terminals.

7. The IC of claim 1, wherein the control signal is a periodic signal.

8. The IC of claim 1, wherein the second circuit is for supplying configuration data sets to the first logic circuit at a particular rate for at least a duration of time.

9. The IC of claim 1, wherein the second circuit comprises a set of selection terminals, wherein the selection terminals receive a portion of the control signal.

10. An integrated circuit (“

IC”

) comprising;

a) a configurable logic circuit comprising a set of configuration inputs; and

b) a via programmed structure comprising a set of vias and potential vias, the via programmed array for connecting a set of input lines to the configuration inputs of the configurable logic circuit;

wherein the IC receives a control signal, wherein the set of input lines receives at least a portion of said control signal;

wherein based on the connected input lines, the first logic circuit performs a first operation during a first time duration and a second operation during a second time duration.

11. The IC of claim 10, wherein the control signal is a periodic signal.

12. The IC of claim 10, wherein the control signal is a clock signal.

13. The IC of claim 10 further comprising a sub-cycle signal generator that generates the control signal.

14. A method of configuring a via programmed logic circuit, the method comprising:

a) identifying a via programmed array (VPA) logic circuit comprising a core logic circuit, a switching circuit, and VPA structure;

b) identifying a plurality of configuration data sets to supply to the core logic circuit; and

c) identifying a set of inputs of the VPA for receiving at least a portion of a control signal; and

d) specifying a set of vias in the VPA structure in order to provide configuration data sets through the switching circuit to the core logic circuit based on said control signal.

15. The method of claim 14, wherein the VPA logic circuit implements functions of a non-VPA logic circuit comprising a core logic circuit and a selection circuit, wherein the core logic circuit, the switching circuit, and the VPA of the VPA logic circuit are identified based on the core logic circuit and the selection circuit of the non-VPA logic circuit.