Apparatus, system, and method for Z-culling

• US 7,450,120 B1
• Filed: 12/19/2003
• Issued: 11/11/2008
• Est. Priority Date: 12/19/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Simeral, Brad W., Hakura, Ziyad S., Cox, Michael Brian, Langendorf, Brian K.
• Primary Examiner(s): Chauhan; Ulka
• Assistant Examiner(s): Prendergast; Roberta
• Application Number:
  US10/741,115
• Time in Patent Office: 1,789 Days
• Field of Search: 345/421, 345/422, 345/503, 345/506, 345/539, 345/519
• US Class Current: 345/421
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/405 using Z-buffer

Abstract

A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Claims

1. A method of forming information on chip for culling tiles of a graphics system, comprising:

on a graphics processing unit, performing rendering of scenes, including performing a second pass of Z-culling on a frame-by-frame basis;

on a coprocessor acting one frame ahead of said graphics processing unit to perform a first pass of Z-culling at a coarse level of resolution, including;

performing a first step of vertex processing to calculate vertex data for rasterization of a current frame being processed by the coprocessor;

performing a first step of rasterization to rasterize the current frame fame being processed by the coprocessor;

constructing a surface of nearest and farthest objects being rendered and determining Z depth data for near and far objects;

determining a Z depth threshold value to perform Z-culling to identify covered tiles to perform the first pass of Z-culling at a coarse level of resolution for the current frame; and

providing coarse Z-cull information to said graphics processing unit to begin the second pass of Z-culling for the current frame;

said coprocessor performing vertex processing, rasterization, and Z-culling on a frame-by-frame basis to process frames identical to those processed by said graphics processing unit but with said coprocessor working one frame ahead of said graphics processing unit and at a coarser level of resolution such that said graphics processing unit begins the processing of a new frame with an initial set of culling information generated by said coprocessor for the same frame.

2. The method of claim 1, wherein said graphics processing unit performs a second step of vertex processing, a second step of rasterization, and a second step of Z-culling for the current frame at a time corresponding to one frame after said coprocessor processes the current frame.

3. The method of claim 1 wherein said first pass of Z-culling comprises:

on said coprocessor, rasterizing primitives at a coarse level of resolution and generating Znear data for tiles, where Znear is a conservative estimate of a nearest Z value of a tile with respect to an eyepoint;

on said coprocessor, for each incoming primitive, comparing Z depth values of incoming tiles of said primitive with previously observed Znear values for tiles with the same tile location and Zfar values tiles with the same tile location to generate information for determining tiles to be culled;

on said coprocessor, rasterizing primitives at a fine level of resolution to generate Zfar data for graphical primitives at a fine level of resolution at least as small as one pixel in resolution; and

on said coprocessor, forming said Zfar values for tiles by coalescing at least a portion of said Zfar data at said fine level of resolution in an on-chip cache memory to generate tile information which identifies fully covered tiles and a corresponding conservative estimate of a Zfar value for each fully covered tile; and

providing a feedback path to utilize said Zfar values for tiles generated by said coalescing for use in said determining tiles to be culled that is provided to said graphics processing unit to begin said second pass of Z-culling.

4. The method of claim 3, further comprising:

identifying tiles that can be accepted as being non-occluded.

5. The method of claim 3, further comprising:

identifying tiles that can be rejected as being occluded.

6. The method of claim 3, wherein said Z-culling information comprises a z threshold and a mask for identifying tiles that are occluded.

7. An integrated circuit for forming information for Z-culling information, comprising:

a coprocessor including;

a vertex engine to perform vertex processing;

a coarse-raster module configured to receive data from the vertex engine and rasterize primitives at a coarse level of resolution corresponding to tiles having groups of pixels and generate information sufficient to determine a Znear for tiles corresponding to a nearest Z distance of a tile with respect to an eyepoint;

a coarse Z-cull module receiving an output of said raster module, the Z-cull module constructing a surface of nearest and farthest objects being rendered and determining Z depth data for near and far objects to generate information for determining tiles that may be culled by comparing Z depth information of incoming tiles with Znear and Zfar values of previously observed tiles having the same tile location, where Zfar is a farthest Z distance with respect to said eyepoint;

a fine raster module coupled to an output of said Z-cull module configured to generate Zfar values for incoming primitives at a fine resolution corresponding to screen regions at least as small as one pixel in size, each Zfar value corresponding to a conservative estimate of a farthest Z value with respect to an eyepoint; and

an on-chip cache memory configured to coalesce said Zfar values generated from said fine raster module, coalesce coverage masks across samples, generate Zfar values for samples within tiles, and provide a maximum Zfar value for covered tiles to said Z-cull module;

said coprocessor being operative to generate coarse Z cull information for determining tiles capable of being culled;

said coprocessor performing vertex processing, rasterization, and Z-culling on a frame-by-frame basis to process frames identical to those processed by a graphics processing unit but with said coprocessor working one frame ahead of said graphics processing unit and at a coarser level of resolution such that said graphics processing unit begins the processing of a new frame including performing a second pass of z-culling on a frame-by-frame basis, with an initial set of culling information generated by said coprocessor for the same frame.

8. The integrated circuit of claim 7, wherein a coalescence cache is configured to compare Zfar values of incoming tiles with cached Zfar values and perform updates of said coalescence cache to maintain a conservative estimate of Zfar values of samples.

9. The integrated circuit of claim 7, wherein a coalescence cache is configured to coalesce coverage masks for incoming and stored tiles.

10. The integrated circuit of claim 7, wherein said coprocessor and said graphics processing unit are disposed on a common chip.

11. The integrated circuit of claim 7, wherein said coarse Z cull module is configured to generate a threshold Z value for distinguishing occluders within a group of tiles.

12. The integrated circuit of claim 7, wherein said coarse Z cull module is configured to identify a new tile as an occluder in response to a Zfar of said new tile being closer to an eyepoint than a previous Znear value for an (x,y) location of said new tile.

13. The integrated circuit of claim 7, wherein said coarse Z cull module is configured to identify a new tile as an occluded tile in response to a Znear of said new tile being farther away from an eyepoint that a Zfar value in said cache for said (x,y) location of said new tile.

14. The integrated circuit of claim 7, wherein a coalescence cache includes a coalescing policy for performing for an incoming new tile at least one of dropping said new incoming tile, coalescing said new incoming tile with exiting tiles, or creating a new entry for said incoming tile.

15. The integrated circuit of claim 7, wherein said graphics processor performs a second step of vertex processing, a second step of rasterization, and a second step of Z-culling for the current frame at a time corresponding to one frame after said coprocessor processes the current frame.