Pulsed signaling multiplexer

• US 7,450,535 B2
• Filed: 12/01/2005
• Issued: 11/11/2008
• Est. Priority Date: 12/01/2005
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Best, Scott C.
• Primary Examiner(s): Milord; Marceau
• Application Number:
  US11/292,686
• Publication Number:
  US 20070127404A1
• Time in Patent Office: 1,076 Days
• Field of Search: 370/314, 370/205, 370/211, 370/208
• US Class Current: 370/314
• CPC Class Codes: H04J 3/02 Details electronic switching or gating H03K17/00
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission

Abstract

In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter and a second AC-coupled transmitter. The first AC-coupled transmitter includes a first driver having a first input to receive first data and a first output. A first AC-coupling element couples the first output to a common output node. The second AC-coupled transmitter includes a second driver having a second input to receive second data, and a second output. A second AC-coupling element couples the second output to the same first common output node.

Claims

1. A pulsed signaling multiplexer comprising:

a first AC-coupled transmitter, the first AC-coupled transmitter having a first driver having a first input to receive first data and a first output, a first AC-coupling element coupled between the first output and a first common output node;

a second AC-coupled transmitter, the second AC-coupled transmitter having a second driver having a second input to receive second data, and a second output, a second AC-coupling element coupled between the second output and the first common output node; and

timing circuitry coupled to the first and the second AC-coupled transmitters to enable time-multiplexed data output from the first and second AC-coupled transmitters to the common output node.

2. The pulsed signaling multiplexer of claim 1, wherein the timing circuitry is operative to apply phase offsets to the first data and the second data.

3. The pulsed signaling multiplexer of claim 2, wherein the timing circuitry comprises:

a first delay element coupled to the first input, and a second delay element coupled to the second input, each delay element including a clock input; and

a multiphase clock source having a plurality of clock outputs having different phase offsets, each of the plurality of clock outputs coupled to a corresponding delay element clock input.

4. The pulsed signaling multiplexer of claim 3, wherein the delay elements comprise flip-flops.

5. The pulsed signaling multiplexer of claim 3, wherein the multiphase clock source comprises a delay locked loop.

6. The pulsed signaling multiplexer of claim 3, wherein the multiphase clock source comprises a phase locked loop.

7. The pulsed signaling multiplexer of claim 2, wherein the timing circuitry comprises a plurality of programmable delay elements.

8. The pulsed signaling multiplexer of claim 1, wherein the first and second drivers comprise respective first and second inverters.

9. The pulsed signaling multiplexer of claim 1, wherein the first and second AC-coupling elements comprise at least portions of respective first and second series capacitors.

10. The pulsed signaling multiplexer of claim 1, wherein the first and second AC-coupled transmitters are disposed on an integrated circuit.

11. The pulsed signaling multiplexer of claim 10, wherein the integrated circuit comprises a dynamic random access memory.

12. A signal communications apparatus comprising a first plurality of AC-coupled transmitters connected to a first single output terminal, the first plurality of AC-coupled transmitters having respective signal outputs that are multiplexed on the first output terminal and respective AC-coupling elements coupled between the signal outputs and the first output terminal, wherein the AC-coupled transmitters have respective clocks offset in phase to multiplex the respective signal outputs of the AC-coupled transmitters on the first output terminal.

13. The signal communications apparatus of claim 12 comprising a second plurality of AC-coupled transmitters connected to a second single output terminal, the second plurality of AC-coupled transmitters having respective signal outputs which are multiplexed on the second output terminal, wherein the AC-coupled transmitters have respective clocks offset in phase to multiplex the respective signal outputs of the AC-coupled transmitters on the first output terminal.

14. The signal communications apparatus of claim 12 wherein the clocks are offset in equal phase increments.

15. A pulsed signaling system comprising:

a first integrated circuit including

an AC-coupled transmitter circuit further including a pulsed signaling multiplexer,

timing circuitry coupled to the AC-coupled transmitter circuit, the timing circuitry having a clock signal input to receive a clock signal; and

a second integrated circuit coupled to the first integrated circuit, the second integrated circuit including

a clock generator to generate the clock signal.

16. The pulsed signaling system of claim 15 wherein the first integrated circuit comprises a memory device.

17. The pulsed signaling system of claim 16 wherein the memory device comprises a dynamic random access memory.

18. The pulsed signaling system of claim 15 wherein the pulsed signaling multiplexer comprises:

a plurality of AC-coupled transmitters, each AC-coupled transmitter having

a driver having an input and an output,

an AC-coupling element coupled to the output,

wherein the plurality of AC-coupled transmitters are disposed in parallel and coupled to a common output node, and wherein the input to each driver receives data signals offset in phase from signals applied to the other drivers.

19. The pulsed signaling system of claim 15 wherein the second integrated circuit comprises a processor.

20. The pulsed signaling system of claim 19 wherein the processor comprises a memory controller.

21. The pulsed signaling system of claim 15 wherein the clock generator comprises a multi-phase clock source.

22. The pulsed signaling system of claim 21 wherein the multi-phase clock source comprises a delay-locked-loop circuit.

23. The pulsed signaling system of claim 21 wherein the multi-phase clock source comprises a phase-locked-loop circuit.

24. The pulsed signaling system of claim 15 and further including:

a receiver circuit disposed on the second integrated circuit, the receiver circuit having a data input coupled to the AC-coupled transmitter circuit via a transmission line, and a clock output,

wherein the clock generator provides clock signals to the AC-coupled transmitter circuit and the receiver circuit.

25. The pulsed signaling system of claim 15 wherein the first and second integrated circuits are disposed on a common substrate.

26. The pulsed signaling system of claim 15 wherein the first and second integrated circuits are configured as a system-in-package.

27. A method of transmitting a plurality of signals on a first integrated circuit, the method comprising:

providing data signals on a plurality of signal paths;

phase-shifting the data on the plurality of signal paths by applying timing offsets to the data signals on the plurality of signal paths based on phase-shifted clock signals;

feeding the phase-shifted data on the plurality of signal paths to a plurality of AC-coupled transmitters;

generating pulsed representations of the data with the AC-coupled transmitters;

outputting the pulsed representations from the plurality of AC-coupled transmitters to a common output node;

wherein the pulsed representations on the common output node define a time multiplexed data stream.

28. The method according to claim 27 wherein the phase-shifted clock signals are generated by a multi-phase clock disposed on the first integrated circuit.

29. The method according to claim 27 wherein the phase-shifted clock signals are generated by a multi-phase clock disposed on a second integrated circuit.

30. A pulsed signaling multiplexer comprising:

means for providing data signals on a plurality of signal paths;

means for providing phase-shifted clock signals;

means for phase-shifting the data on the plurality of signal paths, based on the phase-shifted clock signals;

means for feeding the phase-shifted data on the plurality of signal paths to a plurality of AC-coupled transmitters;

means for generating pulsed representations of the data with the AC-coupled transmitters;

means for outputting the pulsed representations from the plurality of AC-coupled transmitters to a common output node; and

wherein the pulsed representations on the common output node define a time multiplexed data stream.