On die thermal sensor of semiconductor memory device and method thereof

• US 7,451,053 B2
• Filed: 09/26/2006
• Issued: 11/11/2008
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jeong, Chun-Seok
• Primary Examiner(s): Ramos-Feliciano; Eliseo
• Assistant Examiner(s): Suglo; Janet L
• Application Number:
  US11/527,849
• Publication Number:
  US 20070126471A1
• Time in Patent Office: 777 Days
• Field of Search: 702/71, 702/99, 702/104, 702/130, 374/141, 324/765, 324/158.1, 327/512
• US Class Current: 702/99
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

An on die thermal sensor (ODTS) includes a thermal sensor for outputting a first comparing voltage by detecting a temperature of the semiconductor memory device; a comparing unit for outputting a trimming code by comparing the first comparing voltage with a second comparing voltage and increasing or decreasing a preset digital code in response to the comparing result; and a voltage level adjusting unit for adjusting a voltage level of the second comparing voltage by determining a maximum variation voltage and a minimum variation voltage based on the trimming code and a temperature control code.

Claims

1. An on die thermal sensor (ODTS) of a semiconductor device, comprising:

a thermal sensor for outputting a first comparing voltage by detecting a temperature of the semiconductor memory device;

a comparing unit for outputting a trimming code by comparing the first comparing voltage with a second comparing voltage and increasing or decreasing a preset digital code in response to the comparing result; and

a voltage level adjusting unit for adjusting a voltage level of the second comparing voltage by determining a maximum variation voltage and a minimum variation voltage based on the trimming code and a temperature control code.

2. The ODTS as recited in claim 1, further comprising a decoding unit for outputting the temperature control code by decoding a preset thermal information code.

3. The ODTS as recited in claim 1, wherein the voltage level adjusting unit includes:

an adjuster for outputting the maximum variation voltage and the minimum variation voltage based on the trimming code and a preset reference voltage; and

a digital to analog converter (DAC) for receiving the maximum variation voltage and the minimum variation voltage and determining the voltage level of the second comparing voltage based on one of the temperature control code and a preset thermal information code.

4. The ODTS as recited in claim 3, wherein the maximum variation voltage is a maximum voltage level of the second comparing voltage and the minimum variation voltage is a minimum voltage level of the second comparing voltage.

5. The ODTS as recited in claim 4, wherein the adjuster includes:

a decoder for decoding the trimming code and generating a variation adjusting code;

a voltage adjuster for adjusting voltage levels of the maximum variation voltage and the minimum variation voltage in response to the variation adjusting code and outputting a division voltage based on the adjusted voltage levels of the maximum variation voltage and the minimum variation voltage; and

a comparing controller for comparing the reference voltage with the division voltage and controlling the voltage adjuster based on the compared result.

6. The ODTS as recited in claim 5, wherein the voltage adjuster includes:

an output controller for controlling the maximum variation voltage and the minimum variation voltage in response to an output of the comparing controller;

a variation voltage adjuster for adjusting the voltage levels of the maximum variation voltage and the minimum variation voltage in response to the variation adjusting code; and

a division voltage adjuster for adjusting a voltage level of the division voltage in response to the adjusted voltage levels of the maximum variation voltage and the minimum variation voltage.

7. The ODTS as recited in claim 6, wherein the output controller includes a transistor having a gate receiving the output of the comparing controller and a source-drain path between a power supply voltage terminal and one terminal of the variation voltage adjuster.

8. The ODTS as recited in claim 6, wherein the variation voltage adjuster includes:

a plurality of resistors connected in series; and

a plurality of switching units, each of which is connected in parallel with a corresponding one of the resistors and turned on under the control of the variation adjusting code.

9. The ODTS as recited in claim 8, wherein each of the switching units includes a transfer gate which is turned on in response to the variation adjusting code.

10. The ODTS as recited in claim 5, wherein the DAC includes:

a first bias determination unit for determining a voltage level of a first bias voltage by comparing a first output voltage with the minimum variation voltage, wherein a voltage level of the first output voltage is controlled by the voltage level of the first bias voltage;

a second bias determination unit for determining a voltage level of a second bias voltage by comparing a second output voltage with the maximum variation voltage, wherein a voltage level of the second output voltage is controlled by the voltage level of the second bias voltage; and

a second comparing voltage determination unit, enabled under the control of one of the preset thermal information code and the temperature control code, for determining the voltage level of the second comparing voltage based on the first and second bias voltages.

11. The ODTS as recited in claim 10, wherein the first bias determination unit includes:

a current mirror circuit for determining the voltage level of the first output voltage based on the first bias voltage; and

a comparator for outputting the first bias voltage by comparing the first output voltage with the minimum variation voltage.

12. The ODTS as recited in claim 10, wherein the second bias determination unit includes:

a current mirror circuit for determining the voltage level of the second output voltage based on the second bias voltage; and

a comparator for outputting the second bias voltage by comparing the second output voltage with the maximum variation voltage.

13. The ODTS as recited in claim 10, wherein the second comparing voltage determination unit includes a current mirror circuit, enabled under the control of one of the thermal information code and the temperature control code, for determining the voltage level of the second comparing voltage based on the first and second bias voltages.

14. The ODTS as recited in claim 1, wherein the comparing unit includes:

a voltage comparator for comparing the first comparing voltage with the second comparing voltage to output a code control signal; and

a code counter for increasing or decreasing the preset digital code in response to the code control signal output from the voltage comparator, thereby outputting the trimming code.

15. An on die thermal sensor (ODTS) of a semiconductor device, comprising:

a thermal sensor for outputting a first comparing voltage by detecting a temperature of the semiconductor memory device;

a comparing unit for outputting a first trimming code in case of a first test mode and a thermal code in case of a second test mode by comparing the first comparing voltage with a second comparing voltage and increasing or decreasing a preset digital code in response to the comparing result;

a voltage level adjusting unit for determining a maximum variation voltage and a minimum variation voltage based on the first trimming code in case of the first test mode and a preset second trimming code in case of the second test mode, thereby adjusting a voltage level of the second comparing voltage in response to a temperature control code; and

a decoding selection unit for decoding a preset thermal information code in case of the first test mode and the thermal code in case of the second test mode, thereby outputting the temperature control code.

16. The ODTS as recited in claim 15, wherein the voltage level adjusting unit includes:

an adjuster for adjusting voltage levels of the maximum variation voltage and the minimum variation voltage based on the first trimming code in case of the first test mode and the second trimming code in case of the second test mode; and

a digital to analog converter (DAC) for receiving the maximum variation voltage and the minimum variation voltage to determine the voltage level of the second comparing voltage based on the temperature control code.

17. The ODTS as recited in claim 16, wherein the maximum variation voltage is a maximum voltage level of the second comparing voltage and the minimum variation voltage is a minimum voltage level of the second comparing voltage.

18. The ODTS as recited in claim 17, wherein the adjuster includes:

a decoder for generating a variation adjusting code by decoding the first trimming code in case of the first test mode and the second trimming code in case of the second test mode;

a voltage adjuster for adjusting voltage levels of the maximum variation voltage and the minimum variation voltage in response to the variation adjusting code and outputting a division voltage by adjusting the voltage levels of the maximum variation voltage and the minimum variation voltage in response to the variation adjusting code; and

a comparing controller for comparing the reference voltage with the division voltage to control the voltage adjuster based on the compared result.

19. The ODTS as recited in claim 18, wherein the voltage adjuster includes:

an output controller for controlling the generation of the maximum variation voltage and the minimum variation voltage in response to an output of the comparing controller;

a variation voltage adjuster for adjusting the voltage levels of the maximum variation voltage and the minimum variation voltage in response to the variation adjusting code; and

a division voltage adjuster for adjusting a voltage level of the division voltage in response to the adjusted voltage levels of the maximum variation voltage and the minimum variation voltage.

20. The ODTS as recited in claim 19, wherein the output controller includes a transistor having a gate receiving the output of the comparing controller and a source-drain path between a power supply voltage terminal and one terminal of the variation voltage adjuster.

21. The ODTS as recited in claim 19, wherein the variation voltage adjuster includes:

a plurality of resistors connected in series; and

a plurality of switching units, each of which is connected in parallel with a corresponding one of the resistors and turned on under the control of the variation adjusting code.

22. The ODTS as recited in claim 21, wherein each of the switching units includes a transfer gate which is turned on in response to the variation adjusting code.

23. The ODTS as recited in claim 18, wherein the DAC includes:

a first bias determination unit for determining a voltage level of a first bias voltage by comparing a first output voltage with the minimum variation voltage, wherein a voltage level of the first output voltage is controlled by the voltage level of the first bias voltage;

a second bias determination unit for determining a voltage level of a second bias voltage by comparing a second output voltage with the maximum variation voltage, wherein a voltage level of the second output voltage is controlled by the voltage level of the second bias voltage; and

a second comparing voltage determination unit, enabled under the control of one of the preset thermal information code and the temperature control code, for determining the voltage level of the second comparing voltage based on the first and second bias voltages.

24. The ODTS as recited in claim 23, wherein the first bias determination unit includes:

a current mirror circuit for determining the voltage level of the first output voltage based on the first bias voltage; and

a comparator for outputting the first bias voltage by comparing the first output voltage with the minimum variation voltage.

25. The ODTS as recited in claim 23, wherein the second bias determination unit includes:

a current mirror circuit for determining the voltage level of the second output voltage based on the second bias voltage; and

a comparator for outputting the second bias voltage by comparing the second output voltage with the maximum variation voltage.

26. The ODTS as recited in claim 23, wherein the second comparing voltage determination unit includes a current mirror circuit, enabled under the control of one of the thermal information code and the temperature control code, for determining the voltage level of the second comparing voltage based on the first and second bias voltages.

27. The ODTS as recited in claim 15, wherein the comparing unit includes:

a voltage comparator for comparing the first comparing voltage with the second comparing voltage to output a code control signal; and

a code counter for increasing or decreasing the preset digital code in response to the code control signal output from the voltage comparator to thereby output the first trimming code in case of the first test mode and output the thermal code in case of the second test mode.

28. The ODTS as recited in claim 15, wherein the decoding selection unit includes:

a multiplexer for selecting one of the thermal information code and the thermal code in response to a selection signal;

a demultiplexer for outputting the first trimming code to the voltage level adjusting unit in case of the first test mode and the thermal code to the multiplexer in case of the second test mode under the control of the selection signal; and

a decoder for outputting the temperature control code to the voltage level adjusting unit by decoding an output code of the multiplexer.

29. The ODTS as recited in claim 28, wherein the selection signal is enabled in the first test mode and disabled in the second test mode.

30. A method for detecting an on die temperature of a semiconductor memory device, the method comprising the steps of:

(a) outputting a first comparing voltage by detecting temperature variation of the semiconductor memory device;

(b) generating a trimming code by comparing the first comparing voltage with a second comparing voltage and increasing or decreasing a preset digital code in response to the comparing result;

(c) adjusting voltage levels of a maximum variation voltage and a minimum variation voltage based on the trimming code; and

(d) determining a voltage level of the second comparing voltage based on the maximum variation voltage and the minimum variation voltage so that the voltage level of the second comparing voltage is substantially the same as that of the first comparing voltage.

31. The method as recited in claim 30, wherein the maximum variation voltage is a maximum voltage level of the second comparing voltage and the minimum variation voltage is a minimum voltage level of the second comparing voltage.

32. The method as recited in claim 30, further comprising, between the step (a) and the step (b), a step of determining an initial voltage level of the second comparing voltage in response to a temperature control code generated by decoding thermal information.

33. The method as recited in claim 30, wherein the steps (b) to (d) are repeated until the voltage level of the second comparing voltage is substantially the same as that of the first comparing voltage.