Nonvolatile memory wear leveling by data replacement processing

• US 7,451,266 B2
• Filed: 03/19/2007
• Issued: 11/11/2008
• Est. Priority Date: 04/10/2003
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shiraishi, Atsushi, Kanamori, Motoki, Shinagawa, Chiaki
• Primary Examiner(s): Ellis; Kevin
• Assistant Examiner(s): Rutz; Jared I
• Application Number:
  US11/723,334
• Publication Number:
  US 20070186033A1
• Time in Patent Office: 603 Days
• Field of Search: 711/103, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.

Claims

1. A nonvolatile memory device comprising:

an erasable and writable nonvolatile memory; and

a control circuit,

wherein said control circuit performs replacement processing of memory areas according to a prescribed timing,

wherein said replacement processing is accomplished by writing data stored in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of said first memory area,

wherein each said memory area holds rewrite frequency data,

wherein said control circuit references the rewrite frequency data to search for an alternative memory area having a rewrite frequency higher than a rewrite frequency of said first memory area and being closest to an average rewrite frequency based on rewrite frequencies of a plurality of memory areas, and to use the alternative memory area as said second memory area.

2. The nonvolatile memory device according to claim 1,

wherein said control circuit references rewrite frequency data obtained from each of a group of memory areas and searches them for said first memory area.

3. The nonvolatile memory device according to claim 1,

wherein each memory area of said nonvolatile memory is provided with a storage area for storing a distinguishing flag indicating whether or not the area is unused, and wherein said control circuit references said distinguishing flag to search for said unused second memory area.

4. The nonvolatile memory device according to claim 1, wherein said control circuit performs said replacement processing in response to a specific command.

5. The nonvolatile memory device according to claim 1,

wherein said control circuit performs said replacement processing in response to completion of processing of a specific command.

6. The nonvolatile memory device according to claim 1,

wherein, in the event of an instruction by another command after a start of said replacement processing, the ongoing replacement processing is abandoned to give priority to processing of that other command.

7. The nonvolatile memory device according to claim 1,

wherein said control circuit performs said replacement processing in response to rewriting the nonvolatile memory a predetermined number of times.