External memory controller node

• US 7,451,280 B2
• Filed: 05/16/2007
• Issued: 11/11/2008
• Est. Priority Date: 11/22/2002
• Status: Expired due to Term

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Furtek, Frederick Curtis, Master, Paul L.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US11/803,998
• Publication Number:
  US 20070226433A1
• Time in Patent Office: 545 Days
• Field of Search: None
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H04L 67/60 Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources admission control or resource allocation H04L47/70

Abstract

A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

Claims

1. A memory controller for an adaptable computing circuit, the adaptable computing circuit including a programmable network and couplable to a memory, the controller comprising:

a network interface configured to receive a memory request from the network and to send data to and receive data from the network;

a memory interface configured to access a memory to fulfill the memory request;

at least one memory processing circuit coupled to the network interface and to the memory interface, the memory processing circuit configured to provide a read memory access service and a write memory access service; and

wherein the memory interface receives and provides data for the memory request using the read and write memory access service.

2. The controller of claim 1, wherein the memory processing circuit is configured to provide at least one of a retrieve/write (“

peek/poke”

) service, a memory random access service, a point-to-point service, a direct memory access (DMA) service, a message service and a real-time input service.

3. The controller of claim 1, wherein the network interface is further configured to provide flow control with a node in the adaptable computing circuit that has sent the memory request.

4. The controller of claim 1, wherein the read memory access service and write memory access service access multi-dimensional data.

5. A memory controller in an adaptable computing circuit including a programmable network, the controller comprising:

a port configured to receive a memory request from a requesting node, in the adaptable computing circuit wherein the port includes a parameter, the parameter configurable by information in the memory request;

a data address generator configured to generate a memory location for a memory based on the parameter associated with the port; and

a memory processing circuit to receive a memory request from the port and to perform a memory operation using the generated memory location.

6. The memory controller of claim 5, wherein the memory request conforms to a point-to-point protocol from the node.

7. The memory controller of claim 6, wherein the point-to-point protocol request includes one of a burst read or a burst write.

8. The memory controller of claim 6, wherein the memory request conforming to the point-to-point protocol includes a control word to configure the data address generator.

9. The memory controller of claim 5, wherein the memory request conforms to a direct memory access (DMA) protocol from the node.

10. The memory controller of claim 5, wherein the memory request conforms to a real-time input protocol from the node.

11. The memory controller of claim 5, wherein the memory request includes real-time read of streaming data or real-time write of streaming data.

12. The memory controller of claim 5, wherein the port includes a buffer memory to store protocol words received from the requesting node.

13. The memory controller of claim 5, wherein the memory request includes access to multi-dimensional data.

14. A system for processing memory service requests in an adaptable computing environment, the system comprising:

a memory;

an adaptable computing node, the node configured to generate a memory service request;

an interconnection network coupled to the adaptable computing node, the interconnection network enabling different interconnections to the adaptable computing node; and

a memory controller configured to receive the memory service request, the memory controller configured to service the memory service request by reading data from or writing data to the memory based on the memory service request, and the memory controller further configured to provide a retrieve/write (“

peek/poke”

) service, a memory random access service, a point-to-point service, a direct memory access service, a messaging service and a real-time input service.

15. A method of accessing external memory via one of a plurality of nodes in a computing system, the computing system an adaptable computing circuit, the adaptable computing circuit having a programmable network couplable to a memory, the method comprising:

configuring a network interface to receive a memory request from the network and to send data to and receive data from the network;

accessing a memory to fulfill the memory request; and

providing a memory access service to receive and provide data for the memory request.

16. The method of claim 15, wherein the memory access service further provides at least one of a retrieve/write (“

peek/poke”

) service, a memory random access service, a point-to-point service, a direct memory access service, a message service and a real-time input service.

17. The method of claim 15, wherein the network interface is further configured to provide flow control with a node that has sent the memory request.

18. A method of accessing memory via an adaptable computing circuit, the adaptable computing circuit including a programmable network and a node, the method comprising:

sending a memory request from the node;

configuring a port to receive the memory request from the requesting node;

configuring a parameter associated with the port by information in the memory request;

generating a memory location in the memory based on the parameter associated with the port; and

performing a memory operation using the generated memory location via a memory protocol.

19. The method of claim 18, wherein the memory request conforms to a point-to-point protocol from the node.

20. The method of claim 19, wherein the point-to-point protocol request includes one of a burst read or a burst write.

21. The method of claim 19, wherein the memory request conforming to the point-to-point protocol includes a control word to configure a data address generator to generate the memory location.

22. The method of claim 18, wherein the memory request conforms to a direct memory access (DMA) protocol from the node.

23. The method of claim 18, wherein the memory request conforms to a real-time input protocol from the node.

24. The method of claim 18, wherein the memory request includes real-time read of streaming data or real-time write of streaming data.

25. The method of claim 18, wherein the memory operation includes storing a protocol word received from the requesting node in a buffer memory of the port.