Error recovery in asynchronous combinational logic circuits

• US 7,451,384 B2
• Filed: 07/15/2004
• Issued: 11/11/2008
• Est. Priority Date: 07/15/2004
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Erstad, David O., Carlson, Roy M.
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US10/891,654
• Publication Number:
  US 20060033523A1
• Time in Patent Office: 1,580 Days
• Field of Search: 714/797, 714/789, 365/181, 326/35
• US Class Current: 714/797
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs

Abstract

A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.

Claims

1. A system for providing error recovery to an asynchronous logic circuit, comprising in combination:

a plurality of asynchronous register voters for receiving outputs from the asynchronous logic circuit, wherein the plurality of asynchronous register voters provide an output indicating a non-data state value if an inconsistent result is detected; and

a plurality of voter gates for receiving an common input from each of the plurality of asynchronous register voters, wherein the plurality of voter gates compares the common inputs from each of the plurality of asynchronous register voters, wherein the plurality of voter gate provides an output having a same logic level as a majority of the common inputs from the plurality of asynchronous register voters, wherein the output from the plurality of voter gates is representative of the outputs from the asynchronous logic circuit.

2. The system of claim 1, wherein the asynchronous logic circuit is a null convention logic circuit.

3. The system of claim 1, wherein the plurality of asynchronous register voters includes an asynchronous register and a plurality of null conversion logic gates.

4. The system of claim 1, further comprising a means to cause a NULL wave front to propagate through the asynchronous logic circuit after detecting a DATA wave front.

5. The system of claim 4, wherein the means to cause a NULL wave front to propagate through the asynchronous logic circuit is a null convention logic gate connected to the outputs of the asynchronous logic circuit.

6. The system of claim 1, further comprising a counter operable to select one of the plurality of asynchronous register voters to latch the outputs of the asynchronous logic circuit.

7. The system of claim 1, wherein the plurality of voting gates are null convention logic gates.

8. The system of claim 1, wherein the inconsistent result is due to a single event upset.

9. A system for providing error recovery to an asynchronous logic circuit, comprising in combination:

a first asynchronous register for providing inputs to the asynchronous logic circuit;

a plurality of asynchronous register voters for receiving outputs from the asynchronous logic circuit, wherein the plurality of asynchronous register voters provide an output indicating a non-data state value if an inconsistent result is detected;

a plurality of voter gates for receiving a common input from each of the plurality of asynchronous register voters, wherein the plurality of voter gates compares the common inputs from each of the plurality of asynchronous register voters, wherein the plurality of voter gates provide an output having a same logic level as a majority of the common inputs from the plurality of asynchronous register voters; and

a second asynchronous register for receiving the outputs from the plurality of voter gates, wherein the second asynchronous register provides an output representative of the output of the asynchronous logic circuit, wherein inconsistent results are detected and corrected prior to the second asynchronous register providing the output.

10. The system of claim 9, wherein the asynchronous logic circuit is a null convention logic circuit.

11. The system of claim 9, wherein the first and second asynchronous register include a bank of null convention logic gates.

12. The system of claim 9, wherein the plurality of asynchronous register voters includes an asynchronous register and a plurality of null conversion logic gates.

13. The system of claim 9, further comprising a means to cause a NULL wave front to propagate through the asynchronous logic circuit after detecting a DATA wave front.

14. The system of claim 13, wherein the means to cause a NULL wave front to propagate through the asynchronous logic circuit is a null convention logic gate connected to the outputs of the asynchronous logic circuit.

15. The system of claim 13, wherein the asynchronous logic circuit resets itself using data from the first asynchronous register.

16. The system of claim 9, further comprising a counter operable to select one of the plurality of asynchronous register voters to latch the outputs of the asynchronous logic circuit.

17. The system of claim 9, wherein the plurality of voting gates are null convention logic gates.

18. The system of claim 9, wherein the inconsistent result is due to is a single event upset.

19. A method for providing error recovery to an asynchronous logic circuit, comprising in combination:

detecting an inconsistent result;

clearing an asynchronous register voter upon detection of the inconsistent result;

comparing common data outputs of a plurality of asynchronous register voters; and

providing an output of the asynchronous logic circuit based on a majority of the common data outputs from the plurality of asynchronous register voters.

20. The method of claim 19, wherein the asynchronous logic circuit is a null convention logic circuit.

21. The method of claim 19, wherein the inconsistent result is due to a single event upset.

22. The method of claim 19, wherein the plurality of asynchronous register voters includes an asynchronous register and a plurality of null conversion logic gates.

23. The method of claim 19, wherein a voter gate compares the common data outputs of the plurality of asynchronous register voters.

24. The method of claim 23, wherein the voter gate is a null convention logic gate.