Application specific configurable logic IP

• US 7,451,426 B2
• Filed: 07/07/2005
• Issued: 11/11/2008
• Est. Priority Date: 07/07/2005
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Pribbernow, Claus
• Primary Examiner(s): Do; Thuan
• Assistant Examiner(s): Levin; Naum B
• Application Number:
  US11/176,514
• Publication Number:
  US 20070011642A1
• Time in Patent Office: 1,223 Days
• Field of Search: 716 16- 18, 703 14- 16, 326 37- 39
• US Class Current: 716/138
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric, communicatively coupled to the system level configuration controller and the at least one standardized interconnect, for mapping arithmetic functions into standard cells; (5) at least one scalable configurable logic module; and (6) a programmable routing matrix. The system level configuration controller is suitable for selecting a standard for the at least one standardized interconnect, the at least one standardized configuration port, and a number of embedded programmable logic functions, and for controlling the programmable routing matrix.

Claims

1. A method for integrating a configurable logic IP module into an ASIC design flow, comprising:

receiving a specification of an integrated circuit product, said specification including at least one of an application type, an application feature, a target market, a technology to be utilized, performance expected, and embedded IP;

implementing hardware and software partition based on said specification;

obtaining architecture of hardware for said integrated circuit product;

implementing ASIC partition based on said architecture of hardware to obtain ASIC elements and non-ASIC elements;

providing a specification for said configurable logic IP module, said configurable logic IP module including a system level configuration controller, at least one standardized interconnect, at least one standardized configuration port, an embedded programmable logic fabric, at least one scalable configurable logic module, and a programmable routing matrix; and

implementing integration of said configurable logic IP module.

2. The method of claim 1, further comprising:

implementing a RTL design for said ASIC elements to obtain an ASIC RTL; and

implementing RTL enhancements for said configurable logic IP module to obtain a configurable logic IP RTL.

3. The method of claim 2, wherein said ASIC RTL and said configurable logic IP RTL reside in a same source.

4. The method of claim 2, wherein at least part of said ASIC RTL and part of said configurable logic IP RTL are same.

5. The method of claim 2, further comprises implementing synthesis and layout for said configurable logic IP module.

6. The method of claim 5, further comprises building and debugging said configurable logic IP module.

7. The method of claim 6, further comprises releasing said configurable logic IP module to software development.

8. The method of claim 2, further comprising:

performing functional verification on said ASIC elements;

performing timing verification on said ASIC elements; and

performing test verification on said ASIC elements.

9. A computer-readable storage device storing a program for causing a computer to execute a method for integrating a configurable logic IP module into an ASIC design flow, said method comprising:

receiving a specification of an integrated circuit product, said specification including at least one of an application type, an application feature, a target market, a technology to be utilized, performance expected, and embedded IP;

implementing hardware and software partition based on said specification;

obtaining architecture of hardware for said integrated circuit product;

implementing ASIC partition based on said architecture of hardware to obtain ASIC elements and non-ASIC elements;

providing a specification for said configurable logic IP module, said configurable logic IP module including a system level configuration controller, at least one standardized interconnect, at least one standardized configuration port, an embedded programmable logic fabric, at least one scalable configurable logic module, and a programmable routing matrix; and

implementing integration of said configurable logic IP module.

10. The computer-readable medium of claim 9, wherein said method further comprising:

implementing a RTL design for said ASIC elements to obtain an ASIC RTL; and

implementing RTL enhancements for said configurable logic IP module to obtain a configurable logic IP RTL.

11. The computer-readable medium of claim 10, wherein said ASIC RTL and said configurable logic IP RTL reside in a same source.

12. The computer-readable medium of claim 10, wherein at least part of said ASIC RTL and part of said configurable logic IP RTL are same.

13. The computer-readable medium of claim 10, wherein said method further comprises implementing synthesis and layout for said configurable logic IP module.

14. The computer-readable medium of claim 13, wherein said method further comprises building and debugging said configurable logic IP module.

15. The computer-readable medium of claim 14, wherein said method further comprises releasing said configurable logic IP module to software development.

16. The computer-readable medium of claim 10, wherein said method further comprising:

performing functional verification on said ASIC elements;

performing timing verification said ASIC elements; and

performing test verification said ASIC elements.