Method of manufacturing a flash memory device

• US 7,452,773 B2
• Filed: 06/09/2006
• Issued: 11/18/2008
• Est. Priority Date: 06/28/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, Jae-Seung, Ko, Yong-Sun, Kwon, Sung-Un
• Primary Examiner(s): Pham; Thanh V.
• Assistant Examiner(s): SCARLETT, SHAKA S
• Application Number:
  US11/449,848
• Publication Number:
  US 20060292795A1
• Time in Patent Office: 893 Days
• Field of Search: None
• US Class Current: 438/257
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.

Claims

1. A method of manufacturing a flash memory device, comprising:

forming an insulation layer pattern on a substrate comprising a cell region and a peripheral region, the insulation layer pattern comprising openings selectively exposing portions of the substrate;

etching the exposed portions of the substrate to form trenches;

filling the trenches with an insulation material to form trench structures;

removing the insulation layer pattern to expose the surface of the substrate between the trench structures;

forming a tunnel oxide layer on the exposed surface of the substrate;

filling a gap space between the trench structures by forming a first conductive layer on the tunnel oxide layer;

partially removing the trench structures to form trench isolation structures and to form a conductive layer pattern from the first conductive layer;

forming a dielectric layer on the first conductive layer pattern and the trench isolation structures;

forming a doped second conductive layer on the dielectric layer to fill gap space between adjacent elements in the first conductive layer pattern;

removing the second conductive layer, the dielectric layer, the first conductive layer pattern and the tunnel oxide layer in the peripheral region to expose the surface of the substrate;

forming an insulation layer on the exposed surface of the substrate in the peripheral region;

forming a un-doped third conductive layer on the second conductive layer in the cell region, and on the insulation layer and the trench isolation structures in the peripheral region; and

forming a first gate structure in the cell region and a second gate structure in the peripheral region, wherein the first gate structure comprises the tunnel oxide layer, a floating gate electrode corresponding to the first conductive layer pattern, a dielectric layer pattern, and a control gate electrode comprising the second and third conductive layers, and the second gate structure comprising a gate insulation layer corresponding to the insulation layer and a gate conductive layer comprising the third conductive layer.

2. The method of claim 1, wherein the insulation layer pattern comprises a multi-layered structure comprising sequentially formed silicon oxide and silicon nitride layers.

3. The method of claim 1, wherein the first conductive layer comprises a doped polysilicon.

4. The method of claim 3, wherein the first conductive layer has a thickness ranging from about 1,000 Å

to 1,500 Å

.

5. The method of claim 1, wherein the dielectric layer comprises a multi-layered structure comprising an oxide/nitride/oxide layer.

6. The method of claim 5, wherein the dielectric layer has a thickness of ranging from about 150 Å

to 200 Å

.

7. The method of claim 1, wherein the second conductive layer has a thickness ranging from about 0.03 times to 0.5 times that of the first conductive layer.

8. The method of claim 1, wherein the second conductive layer comprises polysilicon.

9. The method of claim 8, wherein the second conductive layer has a thickness ranging from about 30 Å

to 750 Å

.

10. The method of claim 1, wherein the third conductive layer comprises a polysilicon.

11. The method of claim 1, wherein the gate insulation layer comprises a silicon oxide.

12. The method of claim 1, further comprising forming a capping insulation layer on the second conductive layer in the cell region.

13. The method of claim 12, wherein the capping layer comprises a silicon nitride.

14. The method of claim 1, further comprising forming a metal silicide layer on the control gate electrode of the first gate structure, the gate conductive layer of the second gate structure.

15. The method of claim 14, wherein forming the metal silicide layer comprises:

forming a metal layer on the control gate of the first gate structure, and the gate conductive layer of the second gate structure; and

thermally treating the metal layer to react metal in the metal layer with silicon in the control gate electrode and the gate conductive layer.

16. The method of claim 15, wherein the metal layer comprises at least one of material comprising cobalt, tungsten, or tantalum.

17. A method of manufacturing a flash memory device, comprising:

forming an insulation layer pattern on a substrate comprising a cell region and a peripheral region, the insulation layer pattern comprising openings selectively exposing portions of the substrate;

etching the exposed portions of the substrate to form trenches;

filling the trenches with an insulation material to form trench structures;

removing the insulation layer pattern to expose the surface of the substrate between the trench structures;

forming a tunnel oxide layer on the exposed surface of the substrate;

filling a gap space between the trench structures by forming a first conductive layer on the tunnel oxide layer;

partially removing the trench structures to form trench isolation structures and to form a conductive layer pattern from the first conductive layer;

forming a dielectric layer on the first conductive layer pattern and the trench isolation structures;

forming a doped second conductive layer on the dielectric layer to fill gap space between adjacent elements in the first conductive layer pattern;

removing the second conductive layer, the dielectric layer, the first conductive layer pattern and the tunnel oxide layer in the peripheral region to expose the surface of the substrate;

forming an insulation layer on the exposed surface of the substrate in the peripheral region;

forming a un-doped third conductive layer on the second conductive layer in the cell region, and on the insulation layer and the trench isolation structures in the peripheral region;

forming a first gate structure in the cell region and a second gate structure in the peripheral region, wherein the first gate structure comprises the tunnel oxide layer, a floating gate electrode corresponding to the first conductive layer pattern, a dielectric layer pattern, and a control gate electrode comprising the second and third conductive layers, and the second gate structure comprising a gate insulation layer corresponding to the insulation layer and a gate conductive layer comprising the third conductive layer;

doping the control gate and the gate conductive layer with impurities; and

,

forming a silicon nitride capping insulation layer on the second conductive layer in the cell region.

18. The method of claim 17, wherein doping the control gate and the gate conductive layer with the impurities comprises performing at least one ion implantation process.

19. The method of claim 17, further comprising forming a metal silicide layer on the control gate electrode of the first gate structure, the gate conductive layer of the second gate structure.

20. The method of claim 19, wherein forming the metal silicide layer comprises:

forming a metal layer on the control gate of the first gate structure, and the gate conductive layer of the second gate structure; and

thermally treating the metal layer to react metal in the metal layer with silicon in the control gate electrode and the gate conductive layer.