Methods, systems, and apparatus for integrated circuit capacitors in capacitor arrays

• US 7,453,136 B2
• Filed: 10/27/2006
• Issued: 11/18/2008
• Est. Priority Date: 07/22/2003
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Nurminen, Juha Seppo, Hakkarainen, Juha Mikko
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US11/588,530
• Publication Number:
  US 20070046519A1
• Time in Patent Office: 753 Days
• Field of Search: 257/532, 438/396, 716/10
• US Class Current: 257/532
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.

Claims

1. A capacitor array in an integrated circuit, the capacitor array comprising:

a plurality of unit capacitor cells arranged to provide visual symmetry;

a set of N active unit capacitor cells of the plurality of unit capacitor cells having a terminal coupled to a signal path to carry analog signals;

if N is a prime number, the N active unit capacitor cells being arranged to be symmetrically located to form an N-equilateral two-dimensional shape to provide electrical symmetry,

otherwise if N is not a prime number,

the set of N active unit capacitor cells being divided into P subsets of M active unit capacitor cells, the M active unit capacitor cells of each of the P subsets being arranged to be symmetrically located to form an M-equilateral two-dimensional shape in a neighborhood, and

each neighborhood of each M-equilateral two-dimensional shape being separated by one or more dummy unit capacitor cells to avoid encroachment of one neighborhood into another in order to provide electrical symmetry.

2. The capacitor array of claim 1 wherein,

the plurality of unit capacitor cells are arranged in equally spaced apart rows and columns to provide visual symmetry.

3. The capacitor array of claim 1 wherein,

the N-equilateral shape is slightly skewed, and

a predetermined distance of separation is maintained between active cells.

4. The capacitor array of claim 1 wherein,

the unit capacitor cells are integrated circuit capacitors.

5. The capacitor array of claim 4 wherein,

the integrated circuit capacitors are metal oxide semiconductor capacitors.

6. The capacitor array of claim 4 wherein,

the integrated circuit capacitors are thin film capacitors.